1. An integrated chip comprising:
a substrate;
a signal processing control circuit supportably arranged on a first side of the substrate; and
a magnetic sensor element supportably positioned on an opposing side of the substrate.
2. The integrated chip of claim 1, further comprising a plurality of vias connecting the signal processing control circuit to the magnetic sensor element.
3. The integrated chip of claim 1, further comprising a frame coupled to the integrated chip, wherein the frame includes metal traces for electrically connecting the signal processing control circuit with the magnetic sensor element.
4. The integrated chip of claim 3, wherein the metal trace elements are coupled to a plurality of wires.
5. The integrated chip of claim 3, wherein the metal trace elements are coupled to a plurality of solder bumps.
6. The integrated chip of claim 1, further comprising a plurality of metal conductive paths for electrically interconnecting the signal processing control circuit with the magnetic sensor element.
7. The integrated chip of claim 1, further comprising a scratch protection layer located on a circuit interconnection layer and having etched openings therein for receiving an electrically conductive element.
8. The integrated chip of claim 7, wherein the scratch protection layer is a silicon nitride layer.
9. A method for manufacturing a double-sided integrated chip, the method comprising:
arranging a signal processing control circuit on a first surface of the substrate;
arranging a magnetic sensor element on an opposite surface of the substrate; and
electrically connecting the signal processing control circuit with the magnetic sensor element.
10. The method of claim 9, further comprising forming a scratch protection layer over a circuit interconnection layer coupled to and located on the signal processing control circuit.
11. The method of claim 9, wherein electrically connecting the signal processing control circuit with the magnetic sensor element includes forming vias that extend through the substrate.
12. The method of claim 11, wherein electrically connecting the signal processing control circuit with the magnetic sensor element includes forming metal trace elements adjacent the vias.
13. The method of claim 9, wherein electrically connecting the signal processing control circuit with the magnetic sensor element includes connecting a circuit interconnection layer in contact with the signal processing control circuit with a sensor interconnection layer in contact with the magnetic sensor element.
14. The method of claim 9, further comprising:
etching openings in a scratch protection layer that is located on a circuit interconnection layer coupled to and located on the signal processing control circuit; and
attaching the chip to a frame that provides electrical communication between the signal processing control circuit and the magnetic sensor element.
15. A method for manufacturing a double-sided integrated chip, the method comprising:
arranging a signal processing control circuit on a first wafer;
arranging a magnetic sensor element on a second wafer; and
attaching the first wafer and the second wafer to a substrate, wherein the signal processing control circuit is positioned on an opposite of the substrate from the magnetic sensor element.
16. The method of claim 14, wherein arranging the signal processing control circuit on the first wafer includes manufacturing the first wafer at a first location.
17. The method of claim 15, wherein arranging the magnetic sensor element on the second wafer includes manufacturing the second wafer at a second location remote from the first location.
18. The method of claim 14, wherein attaching the first wafer and the second wafer to the substrate includes forming vias that extend through the substrate.
19. The method of claim 14, wherein attaching the first wafer to the second wafer includes inserting the chip into a frame that provides metal trace elements for electrically connecting a circuit connection layer in contact with the signal processing control circuit to a sensor interconnection layer in contact with the magnetic sensor element.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A MEMS transducer comprising:
a substrate; and
a plurality of tapered, transducer beams, each tapered, transducer beam comprising a piezoelectric layer and a pair of electrode layers sandwiching the piezoelectric layer for converting applied pressure to voltage, the tapered, transducer beams each having a beam base, a beam end, and a beam body, with the beam body tapered from the beam base to the beam end and disposed between the beam base and the beam end, the tapered, transducer beams connected in a cantilever arrangement over the substrate by having the beam bases attached to the substrate, the beam ends converging towards a single point, and with each beam body free from the substrate and with each beam end free and unattached.
2. The MEMS transducer of claim 1, wherein a gap defined along a length of adjacent tapered, transducer beams is approximately 1 micron or less.
3. The MEMS transducer of claim 1, wherein the beam bases form a substantially continuous microphone perimeter.
4. The MEMS transducer of claim 1, wherein the MEM transducer is a MEMS microphone, and wherein each tapered, transducer beam comprises a triangle, such that the MEMS microphone comprises a substantially polygonal perimeter.
5. The MEMS transducer of claim 1, wherein at least two of the tapered, transducer beams are electrically coupled together in series.
6. The MEMS transducer of claim 1, wherein the piezoelectric layer extends substantially through a width and a length of a tapered, transducer beam.
7. The MEMS transducer of claim 1, wherein the tapered, transducer beams include two piezoelectric layers and three electrode layers.
8. The MEMS transducer of claim 1, wherein the electrode layers of each tapered, transducer beam are electrically coupled in series by metal traces.
9. The MEMS transducer of claim 1, wherein the piezoelectric layer comprises aluminum nitride, and the electrode layers comprise molybdenum.
10. The MEMS transducer of claim 1, wherein the substrate comprises a plurality of conductive traces.
11. A method comprising:
depositing a first electrode layer on a substrate;
depositing a piezoelectric layer;
depositing a second electrode layer;
patterning the second electrode layer;
patterning the piezoelectric layer;
processing the deposited layers to define a plurality of tapered, transducer beams, each tapered, transducer beam comprising the piezoelectric layer and the first and second electrode layers sandwiching the piezoelectric layer for converting applied pressure to voltage, the tapered, transducer beams each having a beam base, a beam end, and a beam body, with the beam body disposed between the beam base and the beam end;
depositing metal traces;
patterning the metal traces; and
releasing the tapered, transducer beams from the substrate, with the released tapered, transducer beams connected in a cantilever arrangement over the substrate, by having the beam bases attached to the substrate, the beam ends converging towards a single point, and with each beam body free from the substrate and with each bean end free and unattached.
12. The method of claim 11, wherein adjacent tapered, transducer beams define gaps extending through the thickness of the deposited layers.
13. The method of claim 11, wherein a gap between adjacent tapered, transducer beams is approximately 1 micron or less.
14. The method of claim 11, wherein the gaps are micromachined.
15. The method of claim 11, wherein the tapered, transducer beams are defined by two intersecting, linear gaps.
16. The method of claim 11, wherein depositing the metal traces comprises depositing a metal trace to each electrode layer.
17. The method of claim 11, wherein releasing the tapered, transducer beams from the substrate comprises etching the substrate away from the tapered, transducer beams.
18. The method of claim 17, wherein etching the substrate comprises deep reactive-ion etching.
19. The method of claim 11, further comprising growing a thermal oxide layer on the substrate before depositing and patterning the piezoelectric and electrode layers.