1. A system for cooperative graphics processing across a graphics bus comprising:
a computer system comprising:
a system memory;
a graphics bus;
a system memory bus,
a graphics processor coupled to the graphics bus; and
a bridge comprising a fragment processor, the bridge being coupled to the system memory via the system memory bus, and to the graphics processor via the graphics bus,
wherein, the graphics processor and fragment processor are configured to perform a plurality of fragment processing operations cooperatively,
wherein a graphics driver executing on the computer system balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating at least a portion of the plurality of fragment processing to the fragment processor to be performed and allocating a remaining portion of the plurality of fragment processing operations to the graphics processor to be performed,
further wherein, the system memory bus has a greater bandwidth than the graphics bus.
2. The system of claim 1, wherein the plurality of fragment processing operations comprises a plurality of raster operations on graphics data stored in the system memory.
3. The system of claim 1, wherein the graphics data stored in the system memory comprises a frame buffer used by the fragment processor and the graphics processor.
4. The system of claim 1, wherein the plurality of fragment processing operations comprises frame buffer blending on the graphics data in the system memory.
5. The system of claim 1, wherein the plurality of fragment processing operations comprises multi-sample expansion on graphics data received from the graphics processor and store resulting expanded data in the system memory.
6. The system of claim 1, wherein the plurality of fragment processing operations comprises evaluating a Z-plane equation coverage value for a plurality of pixels stored in the system memory, wherein the Z-plane equation coverage value is received from the graphics processor.
7. The system of claim 1, wherein the bridge is a North bridge chipset component of the computer system.
8. The system of claim 1, wherein the graphics processor is configured to use a portion of the system memory for frame buffer memory.
9. The system of claim 1, wherein the graphics processor is detachably coupled to the graphics bus by a connector.
10. The system of claim 1, wherein the graphics bus is an AGP graphics bus.
11. The system of claim 1, wherein the graphics bus is a PCI Express graphics bus.
12. The system of claim 1, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor.
13. The system of claim 1, wherein the system memory is used as frame buffer memory for the computer system.
14. The system of claim 1, wherein an amount of data access latency experienced by performing fragment processing operations in the fragment processor is reduced relative to an amount of data access latency experienced by performing the fragment processing operations in the graphics processor.
15. A bridge for implementing cooperative graphics processing with a graphics processor coupled to the bridge across a graphics bus comprising:
a computer system comprising:
a system memory bus interface comprising a system memory bus;
a graphics bus interface comprising a graphics bus; and
a fragment processor disposed in the bridge coupled to the system memory bus, the fragment processor being configured to perform a plurality of fragment processing operations cooperatively with a graphics processor coupled to the graphics bus,
wherein, a graphics driver executing on the computer system balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating at least a portion of the plurality of fragment processing operations to the fragment processor to be performed and allocating a remaining portion of the plurality of fragment processing operations to the graphics processor to be performed,
further wherein, the system memory bus has a greater bandwidth than the graphics bus.
16. The bridge of claim 15, wherein the plurality of fragment processing operations comprises a plurality of raster operations on graphics data stored in the system memory.
17. The system of claim 15, wherein the bridge is configured to use a frame buffer in the system memory for the processing of graphics data.
18. The system of claim 15, wherein the plurality of fragment processing operations comprises frame buffer blending on the graphics data in the system memory.
19. The system of claim 15, wherein the plurality of fragment processing operations comprises multi-sample expansion on graphics data received from the graphics processor and store resulting expanded data in the system memory.
20. The system of claim 15 wherein the plurality of fragment processing operations comprises evaluating a Z plane equation coverage value for a plurality of pixels stored in the system memory, wherein the Z plane equation coverage value is received from the graphics processor.
21. The system of claim 15, wherein the graphics processor is detachably coupled to the graphics bus by a connector.
22. The system of claim 15, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor.
23. The system of claim 15, wherein the system memory bus is coupled to a system memory, and wherein the system memory is used as frame buffer memory for the computer system.
24. In a bridge of a computer system, a method for cooperatively implementing fragment processing operations with a graphics processor across a graphics bus in a computer system, comprising:
in a computer system, receiving at a fragment processor pre-expanded color values from the graphics processor via the graphics bus, the fragment processor, graphics processor and graphics bus being disposed in the computer system;
performing a multi-sample expansion on the color values resulting in expanded color value graphics data, the multi-sample expansion comprising at least a portion of the fragment processing to be performed cooperatively by the fragment processor and the graphics processor in the computer system across the graphics bus;
storing the expanded color value graphics data into a frame buffer in a system memory through a system memory bus; and
rendering an image to a display, the rendering performed by the graphics processor accessing the expanded color value graphics data in the frame buffer,
wherein, the multi-sample expansion is balanced by a graphics driver executing on the computer system by allocating the portion of the fragment processing to the fragment processor to be performed and allocating a remaining portion of the fragment processing to be performed cooperatively to the graphics processor to be performed,
further wherein, the system memory bus has a greater bandwidth than the graphics bus.
25. The method of claim 24, further comprising:
receiving Z plane equation coverage values from the graphics processor via the graphics bus;
performing a Z plane iteration process to generate iterated Z values for a plurality of pixels;
storing the iterated Z values into the frame buffer; and
rendering the image to the display, the rendering performed by the graphics processor accessing the iterated Z values in the frame buffer.
26. The method of claim 24, wherein the bridge is a North bridge chipset component of the computer system.
27. The method of claim 26, wherein the graphics processor is detachably coupled to the graphics bus by a connector.
28. The method of claim 27, wherein the graphics bus is an AGP graphics bus.
29. The method of claim 27, wherein the graphics bus is a PCI Express graphics bus.
30. The method of claim 24, wherein the graphics driver balances the plurality of fragment processing operations between the fragment processor and the graphics processor by allocating as large a share as possible of the plurality of fragment processing operations to the fragment processor.
31. The method of claim 24, wherein the system memory is used as frame buffer memory for the computer system.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A protective case configured to reversibly receive and retain a tablet computing device, said tablet computing device having a back face and a front face, a touchscreen on its front face, and one or more control buttons and ports on its perimeter walls, said case comprising:
a shell having front and back sides wherein the front side is configured to receive and retain the tablet device while providing user access to the touchscreen and user access to one or more of the control buttons, said shell including a back wall that is configured to cover at least a portion of the back face of the tablet, said back wall including a retention slot;
a front cover that includes a first region that is configured to cover the front face of the tablet device and a contiguously connected second region that is configured to cover at least a portion of the back wall; and
a retention tab being connected to an end section of said second region, wherein said retention tab is adapted to being reversibly inserted into said retention slot and reversibly locked into position on the front side of the shell to create an assembled protective case, such that when the assembled case is in a closed position the front cover is configured to extend over and conceal the touchscreen.
2. The protective case of claim 1, wherein when assembled, the front cover and the shell may pivot relative to one another along the retention slot at the back side of the shell.
3. The protective case of claim 1, wherein said shell is generally in the form of a rectangle and wherein said slot is dimensioned to be defined completely internal to the perimeter of the shell.
4. The protective case of claim 1, wherein said retention tab is glued to said end section of the second region of the front cover such that the retention tab may be twisted in one direction over said second region of the front cover into a first low profile position that is configured to pass through the retention slot and twisted in an opposing direction into a second lock position that is configured so as to prohibit passing through the retention slot.
5. The protective case of claim 4, the end section of the second region of the front cover has more than one fabric layers that are inserted into a slot of the retention tab and glued to a recessed region of the front face thereof.
6. The protective case of claim 1, wherein the retention slot has a surrounding recessed region imparted on the front side of the shell.
7. The protective case of claim 1, wherein when the assembled case is in the open position and the tablet is retained within the shell, the cover is configured to stand the shell up on edge.