What is claimed is:
1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a resist on an object to be etched;
(b) forming in said resist a plurality of holes a pitch of which includes different pitches; and
(c) performing ion implantation on said resist to reduce pitch dependence caused to diameters of said holes.
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of:
(d) between said steps (b) and (c), performing processing for reduction of the diameters of said holes.
3. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a resist on an object to be etched; and
(b) forming a plurality of holes in said resist,
wherein said holes include a first hole of a first pitch and a second hole of a second pitch larger than said first pitch,
said method further comprising the step of:
(c) performing ion implantation on said resist to make the amount of increase in the diameter of said second hole larger than that in the diameter of said first hole.
4. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a resist on an object to be etched;
(b) forming in said resist a plurality of holes having center-to-center distance of not more than 0.5 m between holes and having diameters smaller than a desired diameter, and
(c) performing ion implantation on said resist to increase said diameters of said holes to said desired diameter.
5. The method of manufacturing a semiconductor device according to claim 1, wherein
an ion used for said ion implantation is an ion of an inert gas.
6. The method of manufacturing a semiconductor device according to claim 2, wherein
an ion used for said ion implantation is an ion of an inert gas.
7. The method of manufacturing a semiconductor device according to claim 3, wherein
an ion used for said ion implantation is an ion of an inert gas.
8. The method of manufacturing a semiconductor device according to claim 4, wherein
an ion used for said ion implantation is an ion of an inert gas.
9. The method of manufacturing a semiconductor device according to claim 5, wherein
said ion is an Ar ion.
10. The method of manufacturing a semiconductor device according to claim 6, wherein
said ion is an Ar ion.
11. The method of manufacturing a semiconductor device according to claim 7, wherein
said ion is an Ar ion.
12. The method of manufacturing a semiconductor device according to claim 8, wherein
said ion is an Ar ion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A coupling structure for a multi-layered chip filter, comprising:
at least two overlap portion patterns each overlapped with a pattern formed on a resonator layer stacked therewith to form at least two overlap areas spaced from each other; and
a connecting portion pattern formed by connecting at least three linear lines having a predetermined length to each other to connect the at least two overlap portion patterns to each other.
2. The coupling structure according to claim 1, wherein the at least three linear lines are connected while being orthogonal to each other.
3. The coupling structure according to claim 1, wherein each of the at least two overlap portion patterns is formed to be spaced from each other in a symmetrical structure.
4. The coupling structure according to claim 1, wherein the connecting portion pattern of the coupling structure is formed in a symmetrical shape based on a longitudinal axis defined to penetrate through a center between the at least two overlap portion patterns.
5. The coupling structure according to claim 1, wherein the connecting portion pattern of the coupling structure is formed in a symmetrical shape based on a transversal axis defined to penetrate through the at least two overlap portion patterns.
6. The coupling structure according to claim 1, wherein the connecting portion pattern of the coupling structure is formed in an asymmetrical shape.
7. The coupling structure according to claim 1, wherein the at least two overlap portion patterns have the same width as that of the connecting portion pattern.
8. The coupling structure according to claim 1, wherein the at least two overlap portion patterns have a width larger than that of the connecting portion pattern.
9. The coupling structure according to claim 1, wherein the pattern formed on the resonator layer is configured of two portions spaced from each other, each of the two spaced portions being overlapped with each of the at least two overlap portion patterns.
10. The coupling structure according to claim 9, wherein two portions of the pattern formed on the resonator layer is extendedly formed in a longitudinal direction defined to penetrate through a center between the at least two overlap portion patterns.
11. The coupling structure according to claim 9, wherein two portions of the pattern formed on the resonator layer is extendedly formed in a transversal direction defined to penetrate through the at least two overlap portion patterns.
12. A coupling structure for a multi-layered chip filter, comprising:
a coupling overlapped with each of two portions configuring a resonator pattern formed on a resonator layer stacked therewith and separated from each other to form overlap areas, wherein the coupling is formed by connecting at least three linear lines having a predetermined length while being orthogonal to each other.
13. A multi-layered chip filter, comprising:
a first resonator layer;
a second resonator layer;
a coupling layer between the first resonator layer and the second resonator layer; and
a ground layer, wherein a coupling formed in the coupling layer is configured in a coupling structure according to claim 1.