1. A method for interfacing an information handling system and a display, the method comprising:
rendering display information at an information handling system graphics system in a display format;
communicating the display information through a connector and a cable to a transceiver, the display information communicated through the cable in the display format;
communicating the display information with the transceiver to a display through a wireless network;
obtaining identification information from the display with the transceiver;
forwarding the identification information and an output request from the transceiver to the graphics system through an auxiliary link of the connector; and
initiating display information from the graphics system to the transceiver in response to the identification information and output request.
2. The method of claim 1 wherein communicating the display information through a connector further comprises communicating the display information directly from the graphics system to the transceiver without additional processing of the display information.
3. The method of claim 2 wherein communicating the display information directly further comprises communicating the display information through a PHY-Link port on the graphics system.
4. The method of claim 2 wherein communicating the display information directly further comprises communicating the display information through a PHY layer to a common Link layer.
5. The method of claim 1 further comprising:
receiving the display information at the transceiver in a graphics system format; and
converting the display information at the transceiver into a transceiver format.
6. The method of claim 5 wherein the graphics system format comprises DisplayPort and the transceiver format comprises PCI Express.
7. The method of claim 1 wherein communicating the display information through a connector to a transceiver further comprises communicating the display information through a DisplayPort cable.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of matching data and clock signal delays within receive logic, comprising the steps of:
minimizing setup and hold times of said receive logic;
formulating at least one miniaturized version of a clock buffer located within said receive logic, wherein said at least one miniaturized version of said clock buffer is a scaled down version of said clock buffer, said miniaturized version of said clock buffer having a scaling factor of K, said scaling factor representing a number of said miniaturized clock buffers utilized to minimize negative variations experienced by said clock buffer; and
minimizing negative variations experienced by said clock buffer.
2. The method of claim 1, wherein said receive logic is situated on an application specific integrated circuit.
3. The method of claim 1, wherein said negative variations are selected from a group consisting of process, voltage and temperature.
4. The method of claim 1, wherein said clock buffer is capable of driving a received clock signal to a register located within said receive logic.
5. The method of claim 4, wherein a setup time of said receive logic is represented by the equation:
Tsetup=Treg-setup+1.1\xd7(\u2212Tclk-dly)\u2212Tclk-rte(min)
wherein, Treg-setup is a setup time for said register, Tclk-dly is a delay contributed by said clock buffer, and Tclk-rte(min) is a minimum delay contributed by propagation of said clock signal to said register.
6. The method of claim 4, wherein a hold time of said receive logic is represented by the equation:
Thold=Treg-hold+1.1\xd7(Tclk-dly)+Tclk-rte(max)
wherein, Treg-hold is a hold time for said register, Tclk-dly is a delay contributed by said clock buffer, and Tclk-rte(max) is a maximum delay contributed by propagation of said clock signal to said register.
7. The method of claim 1, wherein said clock buffer provides an amount of delay that slows progression of said clock signal in a path to a register located within said receive logic.
8. A system for matching data and clock signal delays within receive logic, comprising:
means for minimizing setup and hold times of said receive logic;
means for formulating at least one miniaturized version of a clock buffer located within said receive logic, wherein said at least one miniaturized version of said clock buffer is a scaled down version of said clock buffer, said miniaturized version of said clock buffer having a scaling factor of K, said scaling factor representing a number of said miniaturized clock buffers utilized to minimize negative variations experienced by said clock buffer; and
means for minimizing negative variations experienced by said clock buffer.
9. The system of claim 8, wherein said receive logic is situated on an application specific integrated circuit.
10. The system of claim 8, wherein said negative variations are selected from a group consisting of process, voltage and temperature.
11. The system of claim 8, wherein said clock buffer is capable of driving a received clock signal to a register located within said receive logic.
12. The system of claim 11, wherein a setup time of said receive logic is represented by the equation:
Tsetup=Treg-setup+1.1\xd7(\u2212Tclk-dly)\u2212Tclk-rte(min)
wherein, Treg-setup is a setup time for said register, Tclk-dly is a delay contributed by said clock buffer, and Tclk-rte(min) is a minimum delay contributed by propagation of said clock signal to said register.
13. The system of claim 11, wherein a hold time of said receive logic is represented by the equation:
Thold=Treg-hold+1.1\xd7(Tclk-dly)+Tclk-rte(max)
wherein, Treg-hold is a hold time for said register, Tclk-dly is a delay contributed by said clock buffer, and Tclk-rte(max) is a maximum delay contributed by propagation of said clock signal to said register.
14. A system comprising:
a register having a clock input and a data input;
a clock receiver for receiving a clock signal;
at least one clock buffer for driving the clock signal to the register;
a data receiver for receiving a data signal; and
at least one data delay device;
wherein the at least one data delay device is configured to substantially match the delay of the clock signal from the clock receiver to the clock input of the register with the delay of the data signal from the data receiver to the data input of the register; and
wherein each of the at least one data delay device is a scaled down version of the at least one clock buffer with respect to size, power, and load.
15. The system of claim 14, wherein the at least one data delay device is configured to mimic the delay of the at least one clock buffer.
16. The system of claim 14, wherein the number of the at least one data delay device is equal to the number of the at least one clock buffer.
17. The system of claim 14, wherein the delay of the at least one clock buffer is subject to variations, and the at least one data delay device is configured to duplicate the variations.
18. The system of claim 14, further comprising a setup time represented by the equation:
Tsetup=Treg-setup+1.1\xd7(\u2212Tclk-dly)\u2212Tclk-rte(min)
wherein, Treg-setup is a setup time for the register, Tclk-dly is a delay contributed by the at least one clock buffer, and Tclk-rte(min) is a minimum delay contributed by propagation of the clock signal to the register.
19. The system of claim 14, further comprising a hold time represented by the equation:
Thold=Treg-hold+1.1\xd7(Tclk-dly)+Tclk-rte(max)
wherein, Treg-hold is a hold time for the register, Tclk-dly is a delay contributed by the at least one clock buffer, and Tclk-rte(max) is a maximum delay contributed by propagation of the clock signal to the register.