1. A system for implementing Advanced Encryption Standard (AES), the system comprising:
circuitry that stores 256 bytes of data; and
said circuitry replacing a non-zero byte portion of said 256 bytes of data with multiplicative inverse bytes in a Galois field GF(256) and affine transforming at least a portion of said replaced inverse bytes over GF (2).
2. The system according to claim 1, wherein said circuitry affine inverse transforms at least a portion of said affine transformed bytes and multiplicatively inverses at least a portion of said affine inverse transformed bytes over GF(256).
3. The system according to claim 1, wherein said circuitry determines said affine transformation over GF(2) as a matrix multiplication and addition of (1 1 0 0 0 1 1 0).
4. The system according to claim 3, wherein said circuitry implements said matrix multiplication and addition using equation:
y0
y1
y2
y3
y4
y5
y6
y7
=
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
\u2061
x0
x1
x2
x3
x4
x5
x6
x7
+
1
1
0
0
0
1
1
0
5. The system according to claim 1, wherein said circuitry maps at least one zero byte from said 256 bytes to said at least one zero byte portion of said 256 bytes of data, if said 256 bytes comprise at least one zero byte.
6. The system according to claim 1, wherein said circuitry replaces said non-zero byte portion of said 256 bytes with multiplicative inverse bytes in said Galois field GF(256) utilizing a first order polynomial (bx+c) with coefficients from GF(16) in optimal normal basis.
7. The system according to claim 1, wherein said circuitry generates said multiplicative inverse bytes in said GF(256) utilizing an irreducible second order polynomial (x2+Ax+B).
8. The system according to claim 7, wherein said circuitry generates said multiplicative inverse bytes in said GF(256) utilizing a first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B).
9. The system according to claim 8, wherein said circuitry generates said first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B) using equation:
(bx+c)\u22121=b(b2B+bcA+c2)\u22121x+(c+bA)(b2B+bcA+c2)\u22121
10. The system according to claim 1, wherein said circuitry maps a polynomial p(x)=x8+x4+x3+x2+1 in GF(256) to a first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c).
11. The system according to claim 10, wherein said circuitry maps said polynomial p(x)=x8+x4+x3+x2+1 in GF(256) to said first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c) utilizing matrices:
T
\u03b3
\u03b1
=
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
\u2062
\u2003
\u2062
T
\u03b1
\u03b3
=
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
0
0
0
1
0
0
1
12. The system according to claim 10, wherein said circuitry maps said polynomial p(x)=x8+x4+x3+x2+1 in GF(256) utilizing look-up table:
13. A method for implementing Advanced Encryption Standard (AES), the method comprising:
storing 256 bytes of data; and
replacing a non-zero byte portion of said 256 bytes of data with multiplicative inverse bytes in a Galois field GF(256) and affine transforming at least a portion of said replaced inverse bytes over GF (2).
14. The method according to claim 13, further comprising affine inverse transforming at least a portion of said affine transformed bytes and multiplicatively inversing at least a portion of said affine inverse transformed bytes over GF(256).
15. The method according to claim 13, further comprising determining said affine transformation over GF(2) as a matrix multiplication and addition of (1 1 0 0 0 1 1 0).
16. The method according to claim 15, further comprising implementing said matrix multiplication and addition using equation:
y0
y1
y2
y3
y4
y5
y6
y7
=
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
\u2061
x0
x1
x2
x3
x4
x5
x6
x7
+
1
1
0
0
0
1
1
0
17. The method according to claim 13, further comprising mapping at least one zero byte from said 256 bytes to said at least one zero byte portion of said 256 bytes of data, if said 256 bytes comprise at least one zero byte.
18. The method according to claim 13, further comprising replacing said non-zero byte portion of said 256 bytes with multiplicative inverse bytes in said Galois field GF(256) utilizing a first order polynomial (bx+c) with coefficients from GF(16) in optimal normal basis.
19. The method according to claim 13, further comprising generating said multiplicative inverse bytes in said GF(256) utilizing an irreducible second order polynomial (x2+Ax+B).
20. The method according to claim 19, further comprising generating said multiplicative inverse bytes in said GF(256) utilizing a first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B).
21. The method according to claim 20, further comprising generating said first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B) using equation:
(bx+c)\u22121=b(b2B+bcA+c2)\u22121x+(c+bA)(b2B+bcA+c2)\u22121
22. The method according to claim 13, further comprising mapping a polynomial p(x)=x8+x4+x3+x2+1 in GF(256) to a first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c).
23. The method according to claim 22, further comprising mapping said polynomial p(x) x8+x4+x3+x2+1 in GF(256) to said first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c) utilizing matrices:
T
\u03b3
\u03b1
=
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
\u2062
\u2003
\u2062
T
\u03b1
\u03b3
=
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
0
0
0
1
0
0
1
24. The method according to claim 22, further comprising mapping polynomial p(x)=x8+x4+x3+x2+1 in GF(256) utilizing look-up table:
25. A machine-readable storage having stored thereon, a computer program having at least a code section for implementing Advanced Encryption Standard (AES), the at least a code section being executable by a machine to perform steps comprising:
storing 256 bytes of data; and
replacing a non-zero byte portion of said 256 bytes of data with multiplicative inverse bytes in a Galois field GF(256) and affine transforming at least a portion of said replaced inverse bytes over GF (2).
26. The machine-readable storage according to claim 25, further comprising code for affine inverse transforming at least a portion of said affine transformed bytes and multiplicatively inversing at least a portion of said affine inverse transformed bytes over GF(256).
27. The machine-readable storage according to claim 25, further comprising code for determining said affine transformation over GF(2) as a matrix multiplication and addition of (1 1 0 0 0 1 1 0).
28. The machine-readable storage according to claim 27, further comprising code for implementing said matrix multiplication and addition using equation:
y0
y1
y2
y3
y4
y5
y6
y7
=
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
\u2061
x0
x1
x2
x3
x4
x5
x6
x7
+
1
1
0
0
0
1
1
0
29. The machine-readable storage according to claim 25, further comprising code for mapping at least one zero byte from said 256 bytes to said at least one zero byte portion of said 256 bytes of data, if said 256 bytes comprise at least one zero byte.
30. The machine-readable storage according to claim 25, further comprising code for replacing said non-zero byte portion of said 256 bytes with multiplicative inverse bytes in said Galois field GF(256) utilizing a first order polynomial (bx+c) with coefficients from GF(16) in optimal normal basis.
31. The machine-readable storage according to claim 25, further comprising code for generating said multiplicative inverse bytes in said GF(256) utilizing an irreducible second order polynomial (x2+Ax+B).
32. The machine-readable storage according to claim 31, further comprising code for generating said multiplicative inverse bytes in said GF(256) utilizing a first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B).
33. The machine-readable storage according to claim 32, further comprising code for generating said first order polynomial (bx+c) modulo said irreducible second order polynomial (x2+Ax+B) using equation:
(bx+c)\u22121=b(b2B+bcA+c2)\u22121x+(c+bA)(b2B+bcA+c2)\u22121
34. The machine-readable storage according to claim 25, further comprising code for mapping a polynomial p(x)=x8+x4+x3+x2+1 in GF(256) to a first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c).
35. The machine-readable storage according to claim 34, further comprising code for mapping said polynomial p(x)=x8+x4+x3+x2+1 in GF(256) to said first order polynomial with coefficients of GF(16) in optimal normal basis (bx+c) utilizing matrices:
T
\u03b3
\u03b1
=
0
1
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
\u2062
\u2003
\u2062
T
\u03b1
\u03b3
=
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
0
1
1
1
1
0
0
0
0
1
0
0
1
36. The machine-readable storage according to claim 34, further comprising code for mapping said polynomial p(x)=x8+x4+x3+x2+1 in GF(256) utilizing look-up table:
37. A method for implementing Advanced Encryption Standard (AES), the method comprising encrypting data using S-Boxes for byte substitution without utilizing a lookup table, in accordance with AES.
38. The method according to claim 37, further comprising decrypting said encrypted data utilizing said S-Boxes that are used for said encryption without utilizing a lookup table.
39. A system for implementing Advanced Encryption Standard (AES), the system comprising a plurality of S-Boxes that are used for byte substitution while encrypting data in accordance with AES without utilizing a lookup table.
40. The system according to claim 39, wherein said S-Boxes that are utilized for said encryption of said data are used for decryption of said encrypted data, without utilizing a lookup table.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device for extending a furniture leg, comprising
an extension member defined by a top face, a bottom face and a longitudinal bore interconnecting said top and bottom faces, said top and bottom faces separated by an extension member height;
an extension bolt, formed from a single piece, having a top end and a bottom end, said top end defined by an upper threaded post and said bottom end defined by a lower threaded bore, said threads on said upper post extending less than the entire length of said bolt, said upper threaded post defining external threads and an external diameter and said lower threaded bore defines internal threads formed on an internal diameter, said external diameter and threads are cooperatively sized to be engagable with said internal diameter and threads, said extension bolt defining a length that exceeds said extension member height; and
a leveling assembly defined by a foot and a threaded post extending upwardly therefrom, said leveling assembly threaded post configured to engage said lower threaded bore.
2. The device of claim 1, further comprising:
a threaded insert configured to threadedly engaging a bore formed in said leg, said insert comprising an outer threaded surface and an inner threaded bore, said inner threaded bore cooperatively designed to accept said upper threaded post, and further defining an internal diameter and internal threads formed thereon that are both substantially the same as said extension bolt threaded bore internal diameter and internal threads.
3. The device of claim 2, wherein said extension bolt comprises:
a first end terminating in said upper threaded post; and
a second end opposite said first end, said second end comprising a socket formed therein, said lower threaded bore opening into said socket.
4. The device of claim 3, wherein:
said upper threaded post defines a first diameter; and
said extension bolt further defines a non-threaded shaft defining a second diameter, said second diameter differing from said first diameter, said shaft and said threaded post interconnected by a conical shoulder.
5. The device of claim 4, wherein said shaft cooperates with said longitudinal bore to be acceptable within said longitudinal bore.
6. The device of claim 5, wherein said extension member is further defined by a front face opposite a rear face, said front face tapering towards said back face.
7. The device of claim 6, wherein said leveling assembly further comprises a locking member threadedly engaging said leveling assembly threaded post.
8. A furniture leg extension and leveling assembly for use with a furniture leg, said furniture leg defining an outer shape having a profile at its lower end and an internal bore formed therein, comprising:
an extension member defined by a top face and a bottom face, said top face defining an outer shape having a profile substantially identical to said outer shape profile of said lower end of said furniture leg;
an extension bolt, formed from a single piece, inserted through a bore formed in said extension member and threadedly engaging a threaded insert into said leg, said threaded insert defining an internal bore having an internal diameter and internal threads formed on said internal bore; and
a leveling assembly threadedly engaging said extension bolt and further defined by a foot, said leveling assembly defining a threaded post having an external diameter and external threads formed on said post, said insert threaded bore internal diameter and threads and said assembly threaded post external diameter and external threads sized to be threadedly engagable.
9. The assembly of claim 8, wherein:
said threaded insert threadedly engages the bore formed in a leg, said insert comprising an outer threaded surface and an inner threaded bore, said inner threaded bore cooperatively designed to accept said upper threaded post.
10. The assembly of claim 9, wherein said extension bolt comprises:
a first end terminating in said upper threaded post; and
a second end opposite said first end, said second end comprising a socket formed therein, said lower threaded bore opening into said socket.
11. The assembly of claim 10, wherein:
said second end of said extension bolt is defined by a bottom face; and
said socket comprises a wrench-accepting depression formed in said bottom face.
12. The assembly of claim 11, wherein said threaded insert is further defined by a bottom face, said bottom face of said threaded insert further defined by at least one tool-engagable depression in said bottom face of said threaded portion.
13. The assembly of claim 12, wherein said shaft cooperates with said longitudinal bore to be acceptable within said longitudinal bore.
14. The assembly of claim 13, wherein said extension member is further defined by a front face opposite a rear face, said front face tapering towards said back face.
15. The assembly of claim 14, wherein said leveling assembly further comprises a locking member threadedly engaging said leveling assembly threaded post.