1. A method for manufacturing a thermal interface material comprising the steps of:
providing a carbon nanotube array comprising a plurality of carbon nanotubes each having two opposite ends;
forming a composite phase change material by filling clearances in the carbon nanotube array with a paraffin;
cutting the composite phase change material to form a section and bending the ends of the carbon nanotubes, wherein the cutting of the composite phase change material is done along a direction that is at an angle to an alignment direction of the carbon nanotubes and bends the ends of the carbon nanotubes; and
heating the section to a temperature of 60 degrees Celsius until the ends of the carbon nanotubes become unbent and protrude out of the section.
2. The method for manufacturing a thermal interface material in accordance with claim 1, wherein the step of forming the composite phase change material comprising steps of:
immersing the carbon nanotube array into xylene;
putting paraffin into the xylene at 60 degrees Celsius;
evaporating the xylene; and
cooling the paraffin down.
3. The method for manufacturing a thermal interface material in accordance with claim 1, wherein the carbon nanotubes are formed by a chemical vapor deposition method or a deposition method.
4. The method for manufacturing a thermal interface material in accordance with claim 3, wherein a catalyst used in the chemical vapor deposition method is made from a material selected from the group comprising of iron, cobalt, nickel, and palladium.
5. The method for manufacturing a thermal interface material in accordance with claim 3, wherein a carbon source gas used in the chemical vapor deposition method is selected from the group comprising of methane, ethylene, propylene, acetylene, methanol, and ethanol.
6. The method for manufacturing a thermal interface material in accordance with claim 1, wherein the carbon nanotubes are substantially parallel to each other.
7. The method for manufacturing a thermal interface material in accordance with claim 1, wherein a thickness of the section is in a range from about 1 \u03bcm to about 100 \u03bcm.
8. The method for manufacturing a thermal interface material in accordance with claim 1, wherein a content of the carbon nanotubes array in the thermal interface material is in a range from about 0.2% to about 10% by volume.
9. The method for manufacturing a thermal interface material in accordance with claim 1, wherein a content of the carbon nanotubes array in the thermal interface material is about 10% by volume.
10. The method for manufacturing a thermal interface material in accordance with claim 1, wherein a content of the carbon nanotubes array in the thermal interface material is about 0.2% by volume.
11. The method for manufacturing a thermal interface material in accordance with claim 1, wherein the angle is approximately ninety degrees.
12. The method for manufacturing a thermal interface material in accordance with claim 1, wherein after cutting the composite phase change material, the carbon nanotubes in the section are in the shape of a \u201cU\u201d.
13. The method for manufacturing a thermal interface material in accordance with claim 1, wherein after cutting the composite phase change material, the carbon nanotubes in the section are formed in the shape of a \u201cZ\u201d.
14. The method for manufacturing a thermal interface material in accordance with claim 1, wherein bending directions of the ends of the carbon nanotubes varies according to the direction of the cutting of the composite phase change material.
15. A method for manufacturing a thermal interface material comprising the steps of:
providing a composite phase change material comprising of carbon nanotube array comprising a plurality of carbon nanotubes each having two opposite ends and a paraffin filling clearances within the carbon nanotube array;
cutting the composite phase change material to form a section and bending the ends of the carbon nanotubes, wherein the cutting of the composite phase change material bends the ends of the carbon nanotubes and is done along a direction that is at an angle to an alignment direction of the carbon nanotubes; and
heating the section until the ends of the carbon nanotubes become unbent and protrude out of the section.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for detecting defects on a wafer, comprising:
determining locations of all instances of a weak geometry in a design for a wafer, wherein the locations comprise random, aperiodic locations, and wherein the weak geometry comprises one or more features that are more prone to defects than other features in the design;
scanning the wafer with a wafer inspection system to thereby generate output for the wafer with one or more detectors of the wafer inspection system; and
detecting defects in at least one instance of the weak geometry based on the output generated at two or more instances of the weak geometry in a single die on the wafer, wherein said determining and said detecting are performed with one or more computer systems.
2. The method of claim 1, wherein the weak geometry is specified in a window at a point in design coordinate space, and wherein a width and a height of the window are less than or equal to 100 nm.
3. The method of claim 2, wherein instances of the window in the design constitute at least some micro care areas for inspection of the wafer.
4. The method of claim 2, further comprising creating a larger window around the window, wherein features in the larger window are used as a pattern of interest for inspection of the wafer.
5. The method of claim 4, wherein detecting the defects comprises aligning the features in the larger window to patch images in the output.
6. The method of claim 4, further comprising determining design context for the weak geometry based on the features in the larger window.
7. The method of claim 4, further comprising grouping all instances of the pattern of interest that are substantially the same into one bin and all other instances of patterns of interest into one or more other bins.
8. The method of claim 4, further comprising generating a standard reference patch image for the pattern of interest by acquiring an image of at least one instance of the pattern of interest with the wafer inspection system.
9. The method of claim 4, further comprising generating a standard reference patch image for the pattern of interest from multiple image patches acquired by the wafer inspection system corresponding to different locations in a die where the pattern of interest exists.
10. The method of claim 9, wherein generating the standard reference patch image from the multiple image patches comprises aligning the multiple image patches to each other with sub-pixel accuracy and processing the aligned multiple image patches together.
11. The method of claim 4, wherein scanning the wafer and detecting the defects are performed with a wafer inspection recipe, and wherein the method further comprises storing a standard reference patch image for the pattern of interest and any other patterns of interest different than the pattern of interest in the wafer inspection recipe.
12. The method of claim 4, wherein detecting the defects comprises aligning a standard reference patch image for the pattern of interest to the output generated by the wafer inspection system to determine the output corresponding to the pattern of interest and applying one or more defect detection algorithms to only a portion of the output corresponding to the pattern of interest, and wherein the portion of the output corresponds to only the weak geometry in the pattern of interest.
13. The method of claim 4, further comprising generating a standard reference patch image for the pattern of interest and a standard defect image for the weak geometry in the pattern of interest.
14. The method of claim 13, wherein the standard defect image is acquired by scanning an additional wafer of the same design and layer as the wafer with the wafer inspection system and the same imaging conditions used for scanning the wafer.
15. The method of claim 13, wherein detecting the defects comprises comparing the output generated for one instance of the weak geometry with the standard reference patch image and comparing the output generated for the one instance of the weak geometry with the standard defect image.
16. The method of claim 15, wherein detecting the defects further comprises determining that a potential defect is located in the one instance of the weak geometry if the output generated for the one instance of the weak geometry and the standard reference patch image are different and if the output generated for the one instance of the weak geometry and the standard defect image are substantially the same.
17. The method of claim 1, wherein detecting the defects comprises determining aggregated properties for the output generated at said all instances of the weak geometry and determining if the at least one instance of the weak geometry includes a defect based on the aggregated properties.
18. The method of claim 1, wherein detecting the defects comprises determining aggregated properties for the output generated in instances of the weak geometry in only a portion of a die and determining if the at least one instance of the weak geometry includes a defect based on the aggregated properties.
19. A non-transitory computer-readable medium, storing program instructions executable on a computer system for performing a computer-implemented method for detecting defects on a wafer, wherein the computer-implemented method comprises:
determining locations of all instances of a weak geometry in a design for a wafer, wherein the locations comprise random, aperiodic locations, and wherein the weak geometry comprises one or more features that are more prone to defects than other features in the design;
scanning the wafer with a wafer inspection system to thereby generate output for the wafer with one or more detectors of the wafer inspection system; and
detecting defects in at least one instance of the weak geometry based on the output generated at two or more instances of the weak geometry in a single die on the wafer.
20. A system configured to detect defects on a wafer, comprising:
an inspection subsystem configured to scan a wafer to thereby generate output for the wafer with one or more detectors of the inspection subsystem; and
one or more computer subsystems configured for:
determining locations of all instances of a weak geometry in a design for the wafer, wherein the locations comprise random, aperiodic locations, and wherein the weak geometry comprises one or more features that are more prone to defects than other features in the design; and
detecting defects in at least one instance of the weak geometry based on the output generated at two or more instances of the weak geometry in a single die on the wafer.