1. A memory system to correct multi-bit errors in a plurality of addressable memory words comprising:
an integrated circuit comprising an array of memory cells having a plurality of addressable rows and columns;
a first set of gates located in said integrated circuit and coupled to said array of memory cells that provide outputs indicative of the multi-bit errors in a first memory word while said first memory word is under test; and
a circuit located in said integrated circuit and coupled to respective outputs of said first set of gates to accumulate multi-bit errors and determine if a number of errors in said first memory word under test exceeds a maximum number of errors correctable by an error correction code circuit,
said error correction code circuit being disabled while said first set of gates and said circuit are in operation.
2. The memory system of claim 1, further comprising a BIST circuit that provides a test pattern input and a memory address selected for test to said first set of gates.
3. The memory system of claim 2, wherein said inputs from said BIST circuit indicate when data from said first memory word under test is expected to be of a first logic state or a second logic state.
4. The memory system of claim 3, wherein said first set of gates comprise a set of XOR gates, each XOR gate receiving a single bit of said first memory word under test.
5. The memory system of claim 1, wherein said circuit comprises a second set of gates configured to implement an accumulator function, each one of the second set of gates coupled to a respective ones of said outputs of said first set of gates and providing outputs, and a latch coupled to said outputs of said second set of gates.
6. The memory system of claim 5, further comprising a detector circuit coupled to said latch for indicating if more than one bit is failing in said first memory word under test.
7. A method for testing an integrated circuit a memory array for multi-bit errors, the memory array utilizing an error recovery technique to correct errors in each one of a plurality of addressable memory words, said error recovery technique having a maximum number of errors it can correct in a given memory word, comprising the steps of:
providing an integrated circuit comprising the memory array;
writing a first test pattern to the memory array;
comparing and accumulating written test data corresponding to the first test pattern for a first memory word to expected data;
writing a second test pattern to the memory array;
comparing and accumulating written test data corresponding to the second test pattern for the first memory word to expected data;
combining written test data for the first test pattern and the second test pattern;
providing outputs indicative of multi-bit errors in said given memory word when said test data is inconsistent with said expected data; and
determining if the number of multi-bit errors in said first memory word exceed said maximum number of errors correctable by said error recovery technique,
said error recover technique being disabled during said method for testing.
8. The method of claim 7, wherein said test pattern is applied by a BIST circuit.
9. The method of claim 7, wherein said accumulation of written test data reveals multi-bit fails in said first memory word.
10. The method of claim 9, wherein an exhaustive series of test patterns to detect multi-bit errors in the memory system comprises:
Write 0s to all cells;
(i) Read 0, (ii) Write 1, (iii) Read 1 for each address, incrementing through addresses;
(i) Read 1, (ii) Write 0, (iii) Read 0 for each address, incrementing through addresses;
(i) Read 0, (ii) Write 1, (iii) Read 1 for each address, decrementing through addresses;
(i) Read 1, (ii) Write 0, (iii) Read 0 for each address, decrementing through addresses; and
Read 0s from all cells.
11. The method of claim 7, wherein said expected data indicates when data from said given memory word is expected to be of a first logic state or a second logic state.
12. The method according to claim 7, wherein the error recovery technique comprises a combination of error correction codes and word line redundancy.
13. A BIST system that utilizes error correction codes (ECC) to correct single bit errors in a given memory word at a given address, said ECC having a maximum number of errors it can correct in the given memory word, comprising:
a first set of gates coupled to an array of memory cells that accumulates and stores a plurality of memory words, each at a given address, said first set of gates providing bit outputs indicative of multi-bit errors in a given memory word while said given memory word is under test; and
a circuit coupled to respective outputs of said first set of gates, to determine if a number of errors in said given memory word under test exceeds said maximum number of errors correctable by the ECC,
said ECC being disabled while said first set of gates and said circuit are in operation.
14. The BIST system of claim 13, wherein said first set of gates comprise a set XOR gates, each XOR gate receiving a single bit of said given memory word under test.
15. The BIST system of claim 14, wherein said circuit comprises a second set of gates, each coupled to a respective ones of said outputs of said first set of gates and providing outputs, and a latch coupled to said outputs of said second set of gates.
16. The BIST system of claim 15, further comprising a detector circuit coupled to said latch for indicating if more than one bit is failing in said given memory word under test.
17. The BIST system of claim 16, wherein said BIST system provides a plurality of test patterns that reveal multi-bit fails in said given memory word.
18. The BIST system of claim 17, wherein said plurality of test patterns comprises:
Write 0s to all cells;
(i) Read 0, (ii) Write 1, (iii) Read 1 for each address, incrementing through addresses;
(i) Read 1, (ii) Write 0, (iii) Read 0 for each address, incrementing through addresses;
(i) Read 0, (ii) Write 1, (iii) Read 1 for each address, decrementing through addresses;
(i) Read 1, (ii) Write 0, (iii) Read 0 for each address, decrementing through addresses; and
Read 0s from all cells.
19. The memory system according to claim 1, wherein the error recovery technique comprises a combination of error correction codes and word line redundancy.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A housing (1) having two housing modules (2, 3) that are releasably connected to one another,
wherein the housing modules (2, 3) are releasably connected to one another at oppositely located wall regions (2c, 2a) via corresponding pairs of slots (9) and hooks (4) in engagement therewith; and a snap-lock device (5) is provided which locks the housing modules (2, 3) in the connected state in order to prevent unintentional release.
2. The housing (1) according to claim 1, wherein one open side of the housing module (2) is closed off by a cover that is releasably connected to a wall region of the housing module (2), and the cover possesses tabs (7) which engage into corresponding slots (10) of the other housing module (3).
3. The housing (1) according to claim 2, wherein the cover (6) is releasably attached to the wall region (2b) of the associated housing module (2) by way of a snap-lock device (8).
4. The housing (1) according to claim 1, wherein the modules are made entirely or partly of metal or plastic.
5. The housing (1) according to claim 1, wherein the modules are embodied for reception of electrical apparatuses.
6. The housing (1) according to claim 5, wherein the modules are embodied for the reception of a radiant element.
7. The housing according to claim 6, wherein one of said modules includes an opening for receiving said radiant element.
8. The housing according to claim 7, further comprising a radiant element housing releasably secured within said opening, said radiant element disposed within said radiant element housing.
9. The housing (1) according to claim 1, wherein at least one housing module (2, 3) is manufactured from a flat sheet that comprises fold seams (11).
10. The housing (1) according to claim 9, wherein the at least one housing module (3) comprises retention devices for the connection of wall regions (3a, 3b) that are adjacent in the folded state.
11. The housing (1) according to claim 10, wherein the retention device is made up of a tab-shaped element (12) on one wall region (3b) and a slot (13) in a second wall region (3a), adjacent to the first wall region (3b), for receiving the tab-shaped element (12).
12. A radiant element housing, comprising:
a first housing having a base and sidewalls extending upwardly therefrom, said first housing having at least one hook extending outwardly from a first sidewall of said first housing, and a snap-lock device extending outwardly from said first sidewall;
a second housing having a base and sidewalls extending upwardly therefrom, said second housing having a first cutout in a first sidewall, and at least one slot disposed adjacent said first cutout, wherein said at least one hook is removeably secured within said at least one slot and said snap-lock device is retained against an edge of said first cutout, thereby releaseably connecting said first housing to said second housing so that said first sidewall of said first housing is aligned with and adjacent said first cutout, and said second housing having a second cutout disposed in a second sidewall; and
a radiant heating element releaseably secured within said second cutout.