What is claimed is:
1. A heating flange, in particular for preheating air in an intake line leading to an internal combustion engine, said heating flange comprising
at least one heating element for heating the air flowing past said heating element, and
a body for mechanically holding and electrically contacting said heating element,
wherein said body comprises a fastening bow having a substantially U-shaped cross-section, and the heating element comprises at least one substantially U-shaped meander loop which is fixedly connected to the base of said fastening bow.
2. The heating flange according to claim 1, wherein the heating element is electrically insulated from the fastening bow at the base of said bow.
3. The heating flange according to claim 2, wherein a substantially rectangular board consisting of an electrically insulating material, preferably mica, micanite or ceramics, is arranged between the heating element and the base of the fastening bow.
4. The heating flange according to claim 1, wherein the heating element is riveted to the fastening bow at the base of said bow.
5. The heating flange according to claim 1, wherein the heating element is welded to the fastening bow at the base of said bow.
6. The heating flange according to claim 1, wherein the heating element is adapted to be produced from a ferritic iron-chromium-aluminium alloy, preferably Kanthal D.
7. The heating flange according to claim 1, wherein the body of the heating flange additionally comprises a cover through which the heating flange can be connected to the intake line.
8. The heating flange according to claim 7, wherein the fastening bow is connected to the cover in an electrically conductive manner.
9. The heating flange according to claim 7, wherein the fastening bow is electrically insulated from the cover.
10. The heating flange according to claim 1, wherein the legs of the U-shaped meander loop of the heating element are angled at least once in the freestanding area encompassed by the air current.
11. The heating flange according to claim 1, wherein the heating flange comprises a first and a second heating element, said heating elements being arranged such that they are displaced relative to one another in a direction transversely to the U-shaped cross-section of the fastening bow.
12. The heating flange according to claim 11, wherein the legs of the meander loop of the first heating element are angled in the freestanding, air current-encompassed areas thereof in a direction opposite to the direction in which the legs of the meander loop of the second heating element are angled.
13. The heating flange according to claim 1, wherein the fastening bow is provided with openings formed in the flanks thereof and used for allowing the air to be heated to flow in transversely to the opening of the U-shaped cross-section.
14. The heating flange according to claim 1, wherein a switching means is provided for switching the electric power at the heating element on and off.
15. The heating flange according to claim 14, wherein the electric switching means comprises at least one semiconductor device.
16. The heating flange according to claim 15, further comprising at least two separately controllable heating elements which are each connected to a respective switching means for switching the electric power supply on and off.
17. The heating flange according to claim 16, wherein the heating elements have power supplied thereto in a time-shifted manner.
18. The heating flange according to claim 1, wherein the power supply of the heating element is controlled by means of a micro controller.
19. The heating flange according to claim 1, further comprising at least one temperature sensor for detecting respective temperature values occurring, preferably temperature values of the air to be heated.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A switching circuit for improving memory writing timing sequence, the switching circuit being coupled to a memory controller, a first DDR memory bank, and a second DDR memory bank, the switching circuit comprising:
a data writing path for providing a plurality of data segments, wherein each data segment has the same valid window;
a first latch disposed within the data writing path and in communication with the first DDR memory bank, the first latch extending the valid window of the odd numbered data segments of the plurality of data segments; and
a second latch disposed within the data writing path and in communication with the second DDR memory bank, the second latch extending the valid window of the even numbered data segments of the plurality of data segments.
2. The switching circuit of claim 1, further comprising:
a first data selection path for transmitting a first data selection signal to the first DDR memory bank, the first data signal originating from the memory controller; and
a second data selection path for transmitting a second data selection signal to the second DDR memory bank, the second data selection signal originating from the memory controller.
3. The switching circuit of claim 2, further comprising:
a timing sequence controller for using a plurality of logical combinations of the first data selection signal and the second data selection signal to logically control the first latch and the second latch.
4. The switching circuit of claim 2, further comprising:
a first delay circuit disposed in series within the first data selection path, the first delay circuit being used for delaying the first data selection signal for a first predetermined time lag; and
a second delay circuit disposed in series within the second data selection path, the second delay circuit being used for delaying the second data selection signal for a second predetermined time lag.
5. The switching circuit of claim 4, wherein the first predetermined time lag equals the second predetermined time lag.
6. A switching circuit for improving memory writing timing sequence, the switching circuit being coupled to and interposed between to a memory controller, a first memory bank, and a second memory bank, the switching circuit being used for transforming a first set of data segments coming from the memory controller into a second set of memory data segments and transmitting the second set of memory data segments to the memory banks, the rate of transmission of the second set of memory data being less than the rate of transmission of the first set of memory data, the switching circuit comprising:
a latch circuit for receiving a latching signal, wherein the latching signal is generated using a logical combination among a plurality of memory selection signals coming from the memory controller, the latching signal controlling the latch circuit to hold the first set of data segments and to output the second set of memory data segments, thereby causing the data valid windows of the second set of memory data segments to be greater than the data valid windows of the first set of data segments.
7. The switching circuit of claim 6, wherein the logical combination includes results of a timing control circuit operating according to the plurality of data selection signals.
8. The switching circuit of claim 6 further comprising a time delay circuit for delaying a data selection signal corresponding to the first set of data segments.
9. A method for improving memory writing timing sequence, the method comprising the steps of:
receiving a plurality of data segments, wherein each data segment has the same data valid window;
extending the data valid windows of the odd numbered data segments of the plurality of data segments and transmitting the same to a first memory; and
extending the data valid windows of the even numbered data segments of the plurality of data segments and transmitting the same to a second memory.
10. The method of claim 9 further comprising delaying a data signal for a predetermined time segment, the data signal corresponding to the extending of data valid windows of the odd numbered data segments of the plurality of data segments and transmitting the same to a first memory.
11. The method of claim 9 further comprising delaying a data signal for a predetermined time segment, the data signal corresponding to the extending of data valid windows of the even numbered data segments of the plurality of data segments and transmitting the same to a second memory.