1. A field effect transistor (FET) comprising:
a plurality of trenches extending into a semiconductor region;
a shield electrode in a lower portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;
an inter-electrode dielectric (IED) over the shield electrode in each trench;
a body region extending between each pair of adjacent trenches;
a gate electrode recessed in an upper portion of each trench over the IED, the gate electrode being insulated from corresponding body regions by a gate dielectric;
source regions in each body region adjacent to the trenches, the source regions having a conductivity type opposite to that of the body regions;
a first interconnect layer contacting the source and body regions; and
a dielectric material insulating each gate electrode and the second interconnect layer from one another,
wherein the plurality of trenches extend in an active region of the FET, the shield electrode and gate electrode extending out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer, and the electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.
2. The FET of claim 1 further comprising:
a substrate; and
a drift region bounded by the body regions and the substrate, wherein the plurality of trenches terminate within the drift region.
3. The FET of claim 1 further comprising:
a substrate; and
a drift region bounded by the body regions and the substrate, wherein the plurality of trenches extend through the drift region and terminate within the substrate.
4. The FET of claim 1 wherein the shield electrode and the gate electrode in each trench are electrically connected together by an additional connection through the IED in each trench.
5. The FET of claim 1 wherein the first interconnect layer is a source interconnect layer, and the second interconnect layer is a gate interconnect layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid crystal display (LCD) device comprising:
first and second substrates facing each other at a predetermined distance;
gate and data lines crossing each other on the first substrate, to define a pixel region;
a first common line substantially parallel to the gate line;
a thin film transistor where the gate and data lines cross;
a first insulating interlayer on an entire surface of the first substrate including the thin film transistor;
an insulating layer having walls over the gate and data lines;
a second common line and a common electrode in the pixel region extending in one direction and overlapping the gate line, the data line and the thin film transistor;
a pixel electrode in contact with a drain electrode of the thin film transistor and between the common electrodes of the pixel region at fixed intervals; and
wherein the walls of the insulating layer are above the gate line at the lower side of the pixel region and some portions of the both data lines adjacent to the pixel region.
2. The LCD device of claim 1, wherein the insulating layer having the walls is formed of an organic insulating layer having a low dielectric constant, including one of photo acryl, polyimide, and BCB (BenzoCycloButene).
3. The LCD device of claim 1, wherein the wall is formed at a height corresponding to a cell gap.
4. The LCD device of claim 1, wherein the wall of the insulating layer may be formed as one pixel unit.
5. The LCD device of claim 1, wherein the wall of the insulating layer may be formed as several tens to hundreds of pixel units.
6. The LCD device of claim 1, wherein the common electrode is formed in the same direction as the insulating layer having the walls above the data line, and the data line in one portion of the pixel region.
7. The LCD device of claim 1, wherein the second common line, the common electrode, and the pixel electrode are formed on the same layer.
8. The LCD device of claim 1, wherein the second common line, the common electrode, and the pixel electrode are formed of one of ITO (Indium-Tin-Oxide), TO (Tin-Oxide), IZO (Indium-Zinc-Oxide) and ITZO (Indium-Tin-Zinc-Oxide).
9. The LCD device of claim 1, further comprising a storage electrode extending from the drain electrode on the first common line.
10. The LCD device of claim 1, wherein the pixel electrode is in contact with the drain electrode and the storage electrode.
11. The LCD device of claim 8, wherein the pixel electrode is in contact with the drain electrode and the storage electrode.
12. A liquid crystal display (LCD) device comprising:
first and second substrates facing each other;
gate and data lines crossing each other on the first substrate, to define a pixel region;
a first common line substantially parallel to the gate line on the same layer, and formed along both lower sides of the adjacent data line at fixed intervals;
a thin film transistor where the gate and data lines cross;
a first insulating interlayer on an entire surface of the first substrate including the thin film transistor;
an insulating layer having walls over the gate and data lines;
a second common line and a common electrode in the pixel region extending in one direction and overlapping the gate line, the data line and the thin film transistor; and
a pixel electrode in contact with a drain electrode of the thin film transistor and between the common electrodes at fixed intervals; and
wherein the walls of the insulating layer are above the gate line at the lower side of the pixel region and some portions of the both data lines adjacent to the pixel region, each wall having a height corresponding to a cell gap.
13. The LCD device of claim 12, wherein the insulating layer having the walls is formed of an organic insulating layer having a low dielectric constant, including one of photo acryl, polyimide, and BCB (BenzoCycloButene).
14. A method for fabricating a liquid crystal display (LCD) device comprising:
forming a gate line having a gate electrode at one side of a substrate;
forming a first common line substantially parallel to the gate line;
forming a gate insulating layer on an entire surface of the substrate including the gate line;
forming an active layer over the gate electrode;
forming a data line substantially perpendicular to the gate line, to define a pixel region;
forming source and drain electrodes overlapping both sides of the active layer;
forming a first insulating interlayer on the entire surface of the substrate including the data line;
forming an insulating layer having walls above the gate and data lines;
forming a second common line and a common electrode in the pixel region extending in one direction, and overlapping the gate line, the data line, and the thin film transistor; and
forming a pixel electrode in contact with a drain electrode of the thin film transistor, and between the common electrodes at fixed intervals; and
wherein the walls of the insulating layer are above the gate line at the lower side of the pixel region and some portions of the both data lines adjacent to the pixel region.
15. The method of claim 14, wherein the process of forming the insulating layer having the walls includes the steps of:
depositing the insulating layer on the first insulating interlayer; and
etching the insulating layer by using a diffraction exposure mask having a slit.
16. The method of claim 15, wherein, when forming the insulating layer using a negative type photosensitive material, the diffraction exposure mask has a closed part corresponding to the wall, and a slit pattern corresponding to the insulating layer, and a transmission part corresponding to the remaining portions.
17. The method of claim 15, wherein, when forming the insulating layer using a positive type photosensitive material, the diffraction exposure mask has a transmission part corresponding to the wall, a slit pattern corresponding to the insulating layer, and a closed part corresponding to the remaining portions.
18. The method of claim 14, wherein the wall of the insulating layer has a height corresponding to a cell gap.
19. The method of claim 14, wherein the insulating layer having the walls is formed using one of a printing method and a method using a soft mold.
20. The method of claim 14, wherein the insulating layer having the walls is formed of an organic insulating layer having a low dielectric constant, including one of photo acryl, polyimide, and BCB (BenzoCycloButene).
21. The method of claim 14, wherein the second common line, the common electrode and the pixel electrode are formed on the same layer, and formed of one of ITO (Indium-Tin-Oxide), TO (Tin-Oxide), IZO (Indium-Zinc-Oxide) and ITZO (Indium-Tin-Zinc-Oxide).
22. The method of claim 14, wherein the first common line is substantially parallel to the gate line on the same layer, and extends substantially perpendicular along both lower sides of the adjacent data line at fixed intervals.