1. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
a dynamic to static conversion unit for a read output of an SRAM array; and
a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode, without affecting functional performance of the dynamic to static conversion unit, and block the read output of the SRAM array and allow a test signal to pass though in a test mode.
2. The design structure of claim 1, wherein the dynamic to static conversion unit comprises a cross-coupled device.
3. The design structure of claim 2, wherein the integrated test bypass unit comprises a hold buffer that is connected to a clock equivalent leg of the cross-coupled device to control working modes of the bypass unit.
4. The design structure of claim 3, wherein a test signal is sent to the hold buffer and the cross coupled device to choose between a functional mode and a test mode for the dynamic to static conversion unit.
5. The design structure of claim 2, wherein the integrated test bypass unit comprises a complex gate implementation that is connected to the cross-coupled device to select a test input as an output of the dynamic to static conversion unit.
6. The design structure of claim 1, wherein the design structure comprises a netlist.
7. The design structure of claim 1, wherein the design structure resides on a storage medium as a data format for the exchange of layout data of integrated circuits.
8. The design structure of claim 1, wherein the design structure includes at least one of test data, characterization data, verification data, or design specification.
9. An integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for chip logic testing, comprising:
a dynamic to static conversion unit for a read output of an SRAM array; and
a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode, without affecting functional performance of the dynamic to static conversion unit, and block the read output of the SRAM array and allow a test signal to pass though in a test mode.
10. The integrated circuit of claim 9, wherein the dynamic to static conversion unit comprises a cross-coupled device.
11. The integrated circuit of claim 9, wherein the test bypass unit comprises a hold buffer that is connected to a clock equivalent leg of the cross-coupled device to control working modes of the bypass unit.
12. The integrated circuit of claim 11, wherein a test signal is sent to the hold buffer and the cross coupled device to choose between a functional mode and a test mode for the dynamic to static conversion unit.
13. The integrated circuit of claim 9, wherein the integrated test bypass unit comprises a complex gate implementation that is connected to the cross-coupled device to select a test input as an output of the dynamic to static conversion unit.
14. A method for high performance SRAM (Static Random Access Memory) read bypass for chip logic testing, comprising:
providing a dynamic to static conversion unit for a read output of an SRAM array; and
providing a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode, without affecting functional performance of the dynamic to static conversion unit, and block the read output of the SRAM array and allow a test signal to pass though in a test mode.
15. The method of claim 14, wherein the dynamic to static conversion unit comprises a cross-coupled device.
16. The method of claim 14, wherein the test bypass unit comprises a hold buffer that is connected to a clock equivalent leg of the cross-coupled device to control working modes of the bypass unit.
17. The method of claim 16, wherein a test signal is sent to the hold buffer and the cross coupled device to choose between a functional mode and a test mode for the dynamic to static conversion unit.
18. The method of claim 14, wherein the integrated test bypass unit comprises a complex gate implementation that is connected to the cross-coupled device to select a test input as an output of the dynamic to static conversion unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A pulse generating circuit for driving a DC motor, comprising:
a ripple pulse forming circuit for forming and outputting a ripple pulse from a ripple component in an electric current for driving the DC motor;
a first signal generating means for outputting a first signal corresponding to a rotational number of the DC motor based on the electric current for driving the DC motor or on a voltage for driving the DC motor;
a judging circuit for calculating a frequency ratio between the ripple pulse and the first signal and judging whether a deviation of the frequency ratio is greater than a predetermined value compared to a predetermined fixed value; and
a correcting circuit for correcting the outputted ripple pulse when the deviation of the frequency ratio is judged to be greater than the predetermined value and maintaining the outputted ripple pulse when the deviation of the ratio is judged to be equal to or less than the predetermined value.
2. The pulse generating circuit according to claim 1 further comprising:
a clock signal generating circuit for generating a clock signal based on the ripple pulse and the first signal; and
a filtering circuit disposed between the DC motor and the ripple pulse forming circuit for variably filtering a cut-off frequency of the ripple pulse based on the clock signal, wherein the first signal outputting circuit inputs the first signal to the judging circuit as the clock signal.
3. The pulse generating circuit according to claim 1, wherein the judging circuit comprises a first counter circuit for counting a number of pulse of the first signal and resetting the counted value by an input of the ripple pulse and for outputting a correction signal correcting the ripple pulse to the correcting circuit when the counted value exceeds a first predetermined value during a time until the resetting of the counted value.
4. The pulse generating circuit according to claim 3 further comprising a masking circuit disposed between the first counter circuit and the correcting circuit for masking the output of the correction signal from the first counter circuit to the correcting circuit when the ripple pulse is inputted and the inputted ripple pulse is irregular.
5. The pulse generating circuit according to claim 4 further comprising:
a second counter circuit for counting a number of pulse of correction signal; and
a defect detecting circuit for outputting a signal indicating a circuit defect when the value counted by the second counter circuit exceeds a second predetermined value.