1. A corrosion and wear resistant tool steel article produced by hot isostatic compaction of nitrogen gas atomized prealloyed powder particles consisting essentially of, in weight percent:
C: 2.0-3.5;
Si: 1.0 max.;
Mn: 1.0 max.;
Cr: 12.0-16.0;
Mo: 2.0-5.0;
V: 6.0-11.0;
Nb: 2.0-6.0;
Co: 1.5-5.0;
N: 0.05-0.30;
and the balance is essentially iron and incidental impurities.
2. A corrosion and wear resistant tool steel article produced by hot isostatic compaction of nitrogen gas atomized prealloyed powder particles consisting essentially of, in weight percent:
C: 2.7-3.0;
Si: 0.50 max.;
Mn: 0.50 max.;
Cr: 13.5-14.5;
Mo: 3.0-4.0;
V: 8.5-9.5;
Nb: 3.0-4.0;
Co: 2.0-3.0;
N: 0.10-0.20;
and the balance is essentially iron and incidental impurities.
3. The article of claim 1 or claim 2, wherein carbon is balanced with chromium, molybdenum, vanadium, and nitrogen in accordance with:
Cmin=0.4+0.099\xd7(% Cr\u221211)+0.063\xd7% Mo+0.177\xd7% V+0.13\xd7% Nb\u22120.85\xd7% N
Cmax=0.6+0.099\xd7(% Cr\u221211)+0.063\xd7% Mo+0.177\xd7% V+0.13\xd7% Nb\u22120.85\xd7% N.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An electronic pulse width modulator circuit operating from a system supply voltage and having an output terminal, the circuit comprising:
a multiplexer having select terminals, input terminals, a common pre-charge node, and a pre-charge device configured to provide a voltage for the common pre-charge node, the voltage being less than the system supply voltage;
a state machine coupled to the output terminal and to a tap select register, the tap select register further coupled to the multiplexer select terminals;
a clock delay chain having a plurality of delay chain elements and delay chain taps, each delay chain tap coupled to one of the input terminals; and
a pre-charge control circuit coupled to the pre-charge device and to the output terminal, the pre-charge control circuit being configured to operate by delaying an output signal from the output terminal, adjusting the logic polarity of the delayed output signal, and coupling the delayed and adjusted output signal to the pre-charge device.
2. The electronic pulse width modulator of claim 1, wherein the state machine advances a select signal controlled by the tap select register in response to a rising edge on the output terminal.
3. An electronic pulse width modulator circuit operating from a system supply voltage and having an output terminal, the circuit comprising:
a multiplexer having select terminals, input terminals, a common pre-charge node, and a pre-charge device configured to provide a voltage for the common pre-charge node, the voltage being less than the system supply voltage;
a state machine coupled to the output terminal and to a tap select register, the tap select register further coupled to the multiplexer select terminals, wherein the state machine advances a select signal controlled by the tap select register in response to a rising edge on the output terminal, causing a pulldown of the common pre-charge node to terminate;
a clock delay chain having a plurality of delay chain elements and delay chain taps, each delay chain tap coupled to one of the input terminals; and
a pre-charge control circuit coupled to the pre-charge device and to the output terminal, the pre-charge control circuit being configured to operate by delaying an output signal from the output terminal, adjusting the logic polarity of the delayed output signal, and coupling the delayed and adjusted output signal to the pre-charge device.
4. A method for applying a controlled voltage to a common signal node, the method comprising:
in a pulse width modulator having a system voltage, coupling the controlled voltage to the common signal node by means of a pre-charge transistor, the controlled voltage being less than the system voltage; and
coupling a delayed and logically adjusted output signal of the pulse width modulator to a gate terminal of the pre-charge transistor, wherein a delay applied to the output signal is based on a plurality of delay chain elements and selectable delay chain taps.
5. A method of creating a self-timed clock pulse in a pulse width modulator circuit operating from a system supply voltage and having an output terminal, the method comprising:
coupling the output terminal to a common node by means of a buffer circuit operating from the system supply voltage;
pre-charging the common node to a voltage less than the system supply voltage;
discharging the common node by a pulldown in response to one of a plurality select signals and a plurality of delayed clock pulses;
advancing the select signal in response to an edge of a signal on the output terminal, thereby terminating the pulldown of the common terminal;
initiating the pre-charging of the common node in response to the edge of the signal on the output terminal; and
terminating the pre-charge of the common node in response to an edge of the signal on the output terminal of opposite direction to the edge of the signal on the output terminal initiating pre-charge of the common node.
6. The method of claim 5 wherein the edge of the signal on the output terminal responsible for advancing the select signal and initiating the pre-charge of the common node is a rising edge, and the edge of the signal on the output terminal terminating the pre-charge of the common node is a falling edge.