What is claimed is:
1. A spread illuminating apparatus having a rectangular light source disposed close to a side end face of a transparent substrate made of a transparent material, wherein said light source is formed with a bar-like light conductive member made of a transparent material and disposed along and close to at least one side end face of said transparent substrate and a spot-like light source disposed at at least one of both ends of said light conductive member and mounted on a flexible printed circuit board, and said flexible printed circuit board comprises a substrate to mount said spot-like light source on and a cover portion extending from said substrate to cover said spot-like light source and terminals near said spot-like light source thereby electrically insulating those from the surrounding.
2. The spread illuminating apparatus according to claim 1, wherein said cover portion is provided by bending an extension from said substrate.
3. The spread illuminating apparatus according to claim 1 or 2, wherein said cover portion comprises bend portions.
4. The spread illuminating apparatus according to claim 2 or 3, wherein said cover portion has a reinforcing film on its inner surface clear of said bend portions.
5. The spread illuminating apparatus according to claim 4, wherein said reinforcing film is of a material high in thermal conductivity such as copper foil.
6. The spread illuminating apparatus according to claim 4, wherein said reinforcing film is of a material low in transparency.
7. The spread illuminating apparatus according to any one of claims 2 to 6, wherein a cover coating is removed at said bend portions.
8. The spread illuminating apparatus according to any one of claims 1 to 7, wherein a frame is provided which covers said light source and extends passing one side end of said transparent substrate to overhang and fix said transparent substrate, a spot-like light source housing portion to house a spot-like light source disposing portion to dispose said spot-like light source of said flexible printed circuit board is provided at the end of said frame, and a positioning mechanism to position said flexible printed circuit board is provided on said spot-like light source disposing portion.
9. The spread illuminating apparatus according to any one of claims 1 to 7, wherein a frame is provided which covers said light source and extends passing one side end of said transparent substrate to overhang and fix said transparent substrate, a spot-like light source housing portion to house a spot-like light source disposing portion to dispose said spot-like light source of said flexible printed circuit board is provided at the end of said frame, and a preventive mechanism against said flexible printed circuit board pulling out from said spot-like light source housing portion is provided on said spot-like light source disposing portion.
10. The spread illuminating apparatus according to any one of claims 1 to 7, wherein a frame is provided which covers said light source and extends passing one end of said transparent substrate to overhang and fix said transparent substrate, a spot-like light source housing portion to house a spot-like light source disposing portion to dispose said spot-like light source of said flexible printed circuit board is provided at the end of said frame, and an integrated mechanism which positions said flexible printed circuit board and at the same time prevents said flexible printed circuit board from pulling out from said spot-like light source housing portion is provided on said spot-like light source disposing portion.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory device comprising an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation, the bitline biasing circuit operating to provide a negative biasing voltage to the bitline, a magnitude of the negative biasing voltage being inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node.
2. The memory device of claim 1, wherein the bitline biasing circuit comprises:
a capacitor;
a first switching circuit for coupling the capacitor to a positive power supply voltage during a first phase to charge the capacitor; and
a second switching circuit for coupling the capacitor between the memory cell supply voltage node and the bitline during a second phase following the first phase to provide the negative biasing voltage to the bitline.
3. The memory device of claim 2, wherein the first switching circuit comprises first and second switch elements, the first switch element coupling a first conductor of the capacitor to a positive power supply voltage node corresponding to the positive power supply voltage and the second switch element coupling a second conductor of the capacitor to a ground node.
4. The memory device of claim 3, wherein the second switching circuit comprises third and fourth switch elements, the third switch element coupling the first conductor of the capacitor to the memory cell supply voltage node and the fourth switch element coupling the second conductor to the bitline.
5. The memory device of claim 2, wherein the positive power supply voltage is greater than the memory cell supply voltage.
6. The memory device of claim 1, wherein the memory cells are SRAM cells.
7. The memory device of claim 1, wherein the bitline biasing circuit comprises:
a capacitor;
a first switching circuit for coupling the capacitor between a positive power supply voltage node and the memory cell supply voltage node during a first phase to charge the capacitor; and
a second switching circuit for coupling the capacitor to the bitline during a second phase following the first phase to provide the negative biasing voltage to the bitline.
8. The memory device of claim 7, wherein the first switching circuit comprises first and second switch elements, the first switch element coupling a first conductor of the capacitor to the positive power supply voltage node corresponding to the positive power supply voltage and the second switch element coupling a second conductor of the capacitor to the memory cell supply voltage node.
9. The memory device of claim 8, wherein the second switching circuit comprises third and fourth switch elements, the third switch element coupling the first conductor of the capacitor to a ground node and the fourth switch element coupling the second conductor to the bitline.
10. The memory device of claim 7, wherein the positive power supply voltage is greater than the memory cell supply voltage.
11. A SRAM memory device comprising:
an array of SRAM memory cells, each cell having at least one pass gate coupled to a bit line; and
a bitline biasing circuit operating to provide a negative bitline voltage to the bitline during a write operation, a magnitude of the negative biasing voltage being inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node, the bitline biasing circuit including a capacitor and first and second switch circuits, the first switch circuit being operable during a first phase to charge the capacitor and the second switch circuit being operable during a second phase following the first phase to couple the capacitor to the bitline.
12. The memory device of claim 11, wherein:
the first switching circuit couples the capacitor to a positive power supply voltage during the first phase to charge the capacitor;
the second switching circuit couples the capacitor between the memory cell supply voltage node and the bitline during the second phase; and
the positive power supply voltage is greater than the memory cell supply voltage.
13. The memory device of claim 12, wherein the first switching circuit comprises first and second switch elements, the first switch element coupling a first conductor of the capacitor to a positive power supply voltage node corresponding to the positive power supply voltage and the second switch element coupling a second conductor of the capacitor to a ground node.
14. The memory device of claim 13, wherein the second switching circuit comprises third and fourth switch elements, the third switch element coupling the first conductor of the capacitor to the memory cell supply voltage node and the fourth switch element coupling the second conductor to the bitline.
15. The memory device of claim 11, wherein:
the first switching circuit couples the capacitor between a positive power supply voltage node and the memory cell supply voltage node during a first phase to charge the capacitor;
the second switching circuit couples the capacitor to the bitline during the second phase; and
the positive power supply voltage is greater than the memory cell supply voltage.
16. The memory device of claim 15, wherein the first switching circuit comprises first and second switch elements, the first switch element coupling a first conductor of the capacitor to the positive power supply voltage node and the second switch element coupling a second conductor of the capacitor to the memory cell supply voltage node.
17. The memory device of claim 16, wherein the second switching circuit comprises third and fourth switch elements, the third switch element coupling the first conductor of the capacitor to a ground node and the fourth switch element coupling the second conductor to the bitline.
18. A SRAM memory device comprising:
an array of SRAM memory cells, each cell being coupled between a memory cell supply voltage node and a second supply voltage node; and
a biasing circuit for providing a memory cell supply voltage at the memory cell supply voltage node during a read operation, the biasing circuit comprising a capacitor and first and second switch circuits, the first switch circuit being operable during a first phase to charge the capacitor and the second switch circuit being operable during a second phase following the first phase to couple the charged capacitor to a memory cell supply voltage node during the read operation.
19. The SRAM memory device of claim 18, wherein the first switch circuit couples the capacitor to a first power supply for charging the capacitor, and the second switching circuit couples the capacitor in series between a second power supply and the memory cell supply voltage node.