1. A circuit component comprising:
a first substrate; and
a device over said first substrate, wherein said device comprises a second substrate over said first substrate, a first metal bump between said first and second substrates, wherein said first metal bump has a top end contacting said second substrate, a first integrated circuit die over said second substrate, and a second metal bump between said first integrated circuit die and said second substrate, wherein said second metal bump has a top end contacting said first integrated circuit die and a bottom end contacting said second substrate, wherein said first metal bump is connected to a first inputoutput pad of said first integrated circuit die, but not connected to any external circuit of said device and said first substrate.
2. The circuit component of claim 1, wherein said device further comprises a third metal bump between said first and second substrates, wherein said first integrated circuit die comprises a second inputoutput pad connected to said first substrate through said third metal bump.
3. The circuit component of claim 1, wherein at least one of said first metal bump and said second metal bump comprises a solder.
4. The circuit component of claim 1, wherein said first integrated circuit die comprises a DRAM integrated circuit die.
5. The circuit component of claim 1, wherein at least one of said first substrate and said second substrate comprises a ceramic substrate.
6. The circuit component of claim 1, wherein at least one of said first substrate and said second substrate comprises a fiberglass reinforced substrate.
7. The circuit component of claim 1, wherein at least one of said first substrate and said second substrate comprises a semiconductor substrate.
8. The circuit component of claim 1, wherein at least one of said first substrate and said second substrate comprises a glass substrate.
9. The circuit component of claim 1, wherein said first substrate comprises a second integrated circuit die.
10. The circuit component of claim 1, wherein said second substrate comprises a second integrated circuit die.
11. The circuit component of claim 1, wherein said first metal bump is not connected to any external circuit of said device.
12. A circuit component comprising:
a first substrate; and
a device over said first substrate, wherein said device comprises a second substrate over said first substrate, a first metal bump between said first and second substrates, wherein said first metal bump has a top end contacting said second substrate, a first integrated circuit die over said second substrate, and a second metal bump between said first integrated circuit die and said second substrate, wherein said second metal bump has a top end contacting said first integrated circuit die and a bottom end contacting said second substrate, wherein said first metal bump is not connected to any external circuit of said device and said first substrate.
13. The circuit component of claim 12, wherein said device further comprises a third metal bump between said first and second substrates, wherein said first integrated circuit die comprises an inputoutput pad connected to said first substrate through said third metal bump.
14. The circuit component of claim 12, wherein at least one of said first metal bump and said second metal bump comprises a solder.
15. The circuit component of claim 12, wherein said first integrated circuit die comprises a DRAM integrated circuit die.
16. The circuit component of claim 12, wherein at least one of said first substrate and said second substrate comprises a ceramic substrate.
17. The circuit component of claim 12, wherein at least one of said first substrate and said second substrate comprises a fiberglass reinforced substrate.
18. The circuit component of claim 12, wherein at least one of said first substrate and said second substrate comprises a semiconductor substrate.
19. The circuit component of claim 12, wherein at least one of said first substrate and said second substrate comprises a glass substrate.
20. The circuit component of claim 12, wherein said first substrate comprises a second integrated circuit die.
21. The circuit component of claim 12, wherein said second substrate comprises a second integrated circuit die.
22. The circuit component of claim 12, wherein said first metal bump is not connected to any external circuit of said device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor package, comprising:
a die having a bottom surface and a top surface;
a die pad having first and second surfaces, the bottom surface of the die being mounted to the first surface of the die pad;
a plurality of leads, each of the leads having first and second surfaces, at least some of the leads being integrally connected to the die pad;
a conductive strap electrically connected to and extending between the top surface of the die and the first surface of at least one of the leads which is not integrally connected to the die pad; and
an encapsulant material encapsulating the die, at least a portion of the die pad, at least a portion of the conductive strap, and at least a portion of each of the leads such that the second surface of each of the leads is generally co-planar with an exterior surface of the encapsulant material.
2. The semiconductor package of claim 1 wherein a portion of the conductive strap is exposed in the encapsulant material.
3. The semiconductor package of claim 1 wherein at least a portion of the second surface of the die pad is exposed in the encapsulant material.
4. The semiconductor package of claim 1 wherein the conductive strap includes a through hole which is filled with the encapsulant material.
5. The semiconductor package of claim 1, wherein the conductive strap comprises:
a first end portion coupled to the top surface of the die;
a second end portion coupled to the first surface of at least one of the leads; and
a central portion extending between the first and second end portions, the central portion having a through hole formed therein which is filled with the encapsulant material.
6. The semiconductor package of claim 1 wherein each of the leads includes a recessed portion which is adjacent to the second surface thereof and is filled with the encapsulant material.
7. The semiconductor package of claim 1 wherein the die pad has a recessed portion which is adjacent to and extends about the periphery of the second surface thereof, the recessed portion of the die pad being filled with the encapsulant material.
8. The semiconductor package of claim 1 wherein:
the conductive strap includes a flange portion having the lip formed thereon;
a conductive layer is disposed between the flange portion and the top surface of the die and between the lip and the die; and
the conductive layer has a first thickness adjacent to the lip and a second thickness adjacent to the flange portion, the first thickness exceeding the second thickness.
9. The semiconductor package of claim 1 wherein:
each of the leads has a recessed portion formed in the first surface thereof; and
the conductive strap has a foot portion which is disposed in the recessed portion of at least one of the leads.
10. The semiconductor package of claim 1 wherein the conductive strap is secured to the first surface of at least one of the leads by a conductive layer.
11. A semiconductor package, comprising:
a die;
a die pad having first and second surfaces, the die being mounted to the first surface of the die pad;
a plurality of leads, each of the leads having first and second surfaces, at least some of the leads being integrally connected to the die pad;
a conductive strap electrically connected to and extending between the die and the first surface of at least one of the leads which is not electrically connected to the die pad; and
an encapsulant material encapsulating the die, at least a portion of the die pad, at least a portion of the conductive strap, and at least a portion of each of the leads such that a portion of the conductive strap is exposed in and substantially flush with an exterior surface of the encapsulant material, at least a portion of the second surface of the die pad is exposed in and substantially flush with the exterior surface of the encapsulant material, and the second surface of each of the leads is exposed in and substantially flush with the exterior surface of the encapsulant material.
12. The semiconductor package of claim 11 wherein the conductive strap comprises:
a first end portion coupled to the die;
a second end portion coupled to the first surface of at least one of the leads; and
a central portion extending between the first and second end portions, the central portion having a through hole formed therein which is filled with the encapsulant material.
13. The semiconductor package of claim 11 wherein each of the leads has a recessed portion which is adjacent to the second surface thereof and is filled with the encapsulant material.
14. The semiconductor package of claim 11 wherein the die pad has a recessed portion adjacent to and extending about the periphery of the second surface thereof, the recessed portion being filled with the encapsulant material.
15. The semiconductor package of claim 11 wherein:
the conductive strap includes a flange portion having a lip formed thereon;
a conductive layer is disposed between the flange portion of the conductive strap and the die and between the lip and the die; and
the conductive layer has a first thickness adjacent to the lip and a second thickness adjacent to the flange portion, the first thickness exceeding the second thickness.
16. A semiconductor package, comprising:
a die;
a die pad having first and second surfaces, the die being mounted to the first surface of the die pad;
a plurality of leads, each of the leads having first and second surfaces, at least some of the leads being integrally connected to the die pad;
a conductive strap electrically connected to and extending between the die and the first surface of at least one of the leads which is not integrally connected to the die pad; and
an encapsulant material encapsulating the die, at least a portion of the die pad, at least a portion of the conductive strap, and at least a portion of each of the leads such that the second surface of each of the leads is exposed in and substantially flush with an exterior surface of the encapsulant material;
each of the leads having a recessed portion adjacent to the second surface thereof which is filled with the encapsulant material, and the die pad having a recessed portion adjacent to and extending about the periphery of the second surface thereof, the recessed portion of the die pad being filled with the encapsulant material.
17. The semiconductor package of claim 16 wherein the conductive strap comprises a through hole which is filled with the encapsulant material.
18. The semiconductor package of claim 16 wherein at least a portion of the second surface of the die pad is exposed in and substantially flush with the exterior surface of the encapsulant material.