What is claimed is:
1. An apparatus for minimizing the idle time of a computer graphic system using hardware controlled flipping comprising:
an instruction queue for receiving instructions from a system bus;
a graphic engine for receiving the instructions output from said instruction queue and for executing drawing activities;
a flipping instruction queue for receiving flipping instructions from said instruction queue; and
a display controller for controlling the activities of displaying image;
wherein, when said graphic engine is idle and an empty space is available in said flipping instruction queue, said instruction queue transmits the flipping instruction to said flipping instruction queue first and then transmits the sequential instructions other than the flipping instruction to said graphic engine so as to reduce the idle time of said graphic engine.
2. The apparatus for minimizing the idle time of a computer graphic system using hardware controlled flipping of claim 1, wherein said flipping instruction queue outputs a flipping instruction when it receives a vertical trigger signal transmitted from said display controller.
3. The apparatus for minimizing the idle time of a computer graphic system using hardware controlled flipping of claim 1, wherein said flipping instruction queue transmits a full signal to said instruction queue.
4. A method for minimizing the idle time of a computer graphic system using hardware controlled flipping, the method comprising steps of:
receiving instructions from a system bus and storing the instructions by an instruction queue;
receiving graphic instructions from said instruction queue and executing drawing activities by a graphic engine;
receiving and storing flipping instructions from said instruction queue when said graphic engine is idle by a flipping instruction queue; and
executing a flipping activity and outputting a flipping instruction stored in said flipping instruction queue by said flipping instruction queue when said flipping instruction queue has the flipping instruction and detects a vertical trigger signal of a display;
wherein, the flipping instruction is transmitted to said flipping instruction queue in advance and then the sequential instructions other than the flipping instruction are continuously transmitted to said graphic engine so as to reduce the idle time of said graphic engine.
5. The method for minimizing the idle time of a computer graphic system using hardware controlled flipping of claim 4, wherein the method further comprising a step of transmitting a full signal from said flipping instruction queue to said instruction queue.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for processing packet data in a transmitter of a communications system, comprising:
receiving a data unit from a logical channel;
assembling one or more data units from the logical channel into a single payload;
constructing a data block by attaching a sequence number to the payload;
transmitting the data block to the receiver.
2. The method of claim 1, further comprising:
attaching an identifier of the logical channel to the data unit received from the logical channel.
3. The method of claim 1, further comprising:
attaching an identifier of the logical channel to the payload assembled by one or more data units from a same logical channel.
4. A method for processing packet data in a receiver of a communications system, comprising:
establishing a reordering buffer per logical channel;
receiving a data block from a transmitter;
forwarding the data block to the reordering buffer identified by the logical channel identity included in the data block;
determining by the sequence number whether the data block can be delivered;
disassembling the data block into data units if the data block can be delivered;
delivering the disassembled data units to the logical channel associated with the reordering buffer.
5. The method of claim 4, wherein the logical channel identity is included in the payload of the data block.
6. The method of claim 5, wherein a logical channel identity field exists per data unit included in the data block.
7. The method of claim 4, wherein the logical channel identity is included in the header of the data block.
8. The method of claim 7, wherein a logical channel identity field exists per data block.
9. The method of claim 4, wherein the data block is determined to be delivered if it is an in-sequence data block.
10. The method of claim 4, wherein the data block is determined not to be delivered if it is an out-of-sequence data block, and further comprising:
storing the data block in a reordering buffer based on its sequence number.
11. A data transmission method of an HSDPA system comprising:
transmitting, with a transmitter, a Data Block composed of one or more data units originated from a same logical channel;
receiving, with a receiver, the Data Block through a HS-DSCH; and
distributing the Data Block to a predetermined reordering buffer.
12. The data transmission method of claim 11, wherein the Data Block includes a transmission sequence number (TSN) field of which value identifies Data Block and the data unit includes a control traffic (CT) field of which value identifies the logical channel.
13. The data transmission method of claim 12, wherein the distributing the Data Block to the reordering buffer includes:
checking the CT field; and
distributing the Data Block to the reordering buffer based on the value of the CT field.
14. The data transmission method of claim 13 wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
delivering the Data Block to higher layers when the Data Block is determined an in-sequence Data Block based on the value of the TSN field.
15. The data transmission method of claim 13, wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
storing the Data Block in a reordering buffer when the Data Block is determined as an out-of sequence Data Block based on the value of the TSN field.
16. The data transmission method of claim 14, wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
storing the Data Block in a reordering buffer when the Data Block is determined as an out-of sequence Data Block based on the value of the TSN field.
17. The data transmission method of claim 16, wherein the distributing the Data Block to the reordering buffer includes:
waiting until a missed Data Block is received;
reordering the Data Blocks in the reordering buffer if the missed Data Block is received.
18. The data transmission method of claim 11, wherein the Data Block has a transmission sequence number (TSN) field of which value identifies Data Block and a control traffic (CT) field of which value identifies the logical channel.
19. The data transmission method of claim 18, wherein the no data unit has CT field.
20. The data transmission method of claim 19, wherein the distributing the Data Block to the reordering buffer includes:
checking the CT field; and
distributing the Data Block to the reordering buffer based on the value of the CT field.
21. The data transmission method of claim 20, wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
delivering the Data Block to higher layers when the Data Block is determined an in-sequence Data Block based on the value of the TSN field.
22. The data transmission method of claim 20, wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
storing the Data Block in a reordering buffer when the Data Block is determined as an out-of sequence Data Block based on the value of the TSN field.
23. The data transmission method of claim 21, wherein the distributing the Data Block to the reordering buffer includes:
checking the TSN field; and
storing the Data Block in a reordering buffer when the Data Block is determined as an out-of sequence Data Block based on the value of the TSN field.
24. The data transmission method of claim 23, wherein the distributing the Data Block to the reordering buffer includes:
waiting until a missed Data Block is received;
reordering the Data Blocks in the reordering buffer if the missed Data Block is received.
25. A method for processing packet data in a transmitter of a communications system, comprising:
receiving data units from plural logical channels;
assembling one or more data units from one logical channel into a single payload;
constructing a data block by attaching a sequence number to the payload;
transmitting the data block to the receiver.
26. A method for processing packet data in a receiver of a communications system, comprising:
establishing reordering buffers for logical channels respectively;
receiving data blocks from a transmitter;
forwarding the data blocks of same logical channel identity to one of the reordering buffers;
determining by the sequence number of the data blocks whether one of the data block can be delivered;
disassembling the data block into data units if the data block can be delivered;
delivering the disassembled data units to said logical channel.
27. The method of claim 26, wherein the logical channel identity is included in the payload of the data block.
28. The method of claim 26, wherein the logical channel is dedicated to a radio bearer.