What is claimed is:
1. In an FET (Field Effect Transistor) using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
2. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
3. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a first AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
4. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said second GaAs layer, and said second GaAs gate buried layer and a gate electrode contact with each other without any gap.
5. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes undoped layers respectively contacting said first and third AlGaAs layers, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
6. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity or an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and second GaAs gate buried layer and a gate electrode contact each other without any gap.
7. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity or an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth AlGaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
8. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
9. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, said second GaAs gate buried layer and a gate electrode contact each other without any gap.
10. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
11. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said third AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said third AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
12. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
13. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first AlGaAs layer is doped with a high concentration n-type impurity, a second GaAs layer includes an undoped layer contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
14. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer includes undoped layers respectively contacting said first and third AlGaAs layers, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
15. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity and an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.
16. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, a second GaAs layer has a three-layer structure made up of either one of a layer doped with an n-type impurity and an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, said third AlGaAs layer is doped with a high concentration n-type impurity, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.
17. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.
18. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of an undoped layer, a layer doped with a high concentration n-type impurity and an undoped layer, as named from a side contacting said first AlGaAs layer, a fourth GaAs layer includes an undoped layer contacting said third AlGaAs layer and a layer doped with a high concentration n-type impurity and forming a top of said fourth GaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
19. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
20. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three-layer structure made up of a layer doped with an n-type impurity, a layer doped with a high concentration n-type impurity and an n-type doped layer, as named from a side contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode contact each other without any gap.
21. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, and said GaAs gate buried layer and a gate electrode are spaced by a minimum distance guaranteeing a sufficient gate breakdown voltage.
22. In an FET using a semiconductor crystal including at least either an undoped InGaAs channel layer or an undoped GaAs channel layer and a first AlGaAs gate contact layer, a second GaAs gate buried layer, a third AlGaAs layer and a fourth GaAs cap layer sequentially formed on said undoped InGaAs channel layer or said undoped GaAs channel layer, and having a double recess structure formed by using said first and third AlGaAs layers as etching stopper layers, said first and third AlGaAs layers each are doped with a high concentration n-type impurity, a second GaAs layer has a three layer structure made up of a layer doped with an n-type impurity, a layer doped with a high concentration n-type impurity and a layer doped with an n-type impurity, as named from a side contacting said first AlGaAs layer, and said second GaAs gate buried layer and a gate electrode are spaced by a minimum gap guaranteeing a sufficient gate breakdown voltage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A device for curing a photosetting substance in an assembly, such as a pivot assembly or a disk drive motor, having a housing with an interior and an opening to the interior, a shaft mounted inside the interior of the housing such that one of the shaft and the housing is rotatable relative to the other, wherein the photosetting substance is located at interfaces between the housing and the shaft, comprising:
a UV light source for emitting UV light;
a conduit for concentrating light from the light source and directing the light into the opening in the housing to cure the photosetting substance located inside the assembly; and
a beam splitter in the conduit for distributing the light inside the housing.
2. The device of claim 1 wherein the beam splitter is a prism-shaped mirror that reflects an original beam of the light into multiple beams that are essentially orthogonal to the original beam.
3. The device of claim 1 wherein the beam splitter is located at a distal tip of the conduit.
4. A device for curing a photosetting substance, comprising in combination:
an assembly having a housing with an interior and an opening to the interior, a shaft mounted inside the interior of the housing such that one of the shaft and the housing is rotatable relative to the other, and a photosetting substance located at interfaces between the housing and the shaft;
a UV light source for emitting light; and
a conduit for concentrating light from the light source and directing the light into the opening in the housing to cure the photosetting substance located inside the assembly.
5. The device of claim 4, further comprising a beam splitter in the conduit for distributing the light inside the housing.
6. The device of claim 5 wherein the beam splitter is a prism-shaped mirror that reflects an original beam of the light into multiple beams that are essentially orthogonal to the original beam.
7. The device of claim 5 wherein the beam splitter is located at a distal tip of the conduit.
8. The device of claim 4 wherein the opening is a mounting hole in a side of the housing.
9. The device of claim 4, further comprising a plurality of openings in the housing for accepting a plurality of conduits, each of which directs light from the light source into the assembly.
10. The device of claim 4 wherein the interior of the housing and an outer surface of the shaft are smooth polished metal to further enhance the intensity of the light incident on the photosetting substance.
11. A method for curing a photosetting substance located within an assembly, such as a pivot assembly or a disk drive motor, the method comprising:
(a) providing an assembly having a first component with an interior, a second component mounted inside the interior of the first component, an opening in the first component, and a photosetting substance located within the assembly at an interface between the first and second components;
(b)) inserting a conduit into the opening;
(c) concentrating and directing light through the conduit into the opening to cure the photosetting substance; and then
(d) removing the conduit from the assembly.
12. The method of claim 11 wherein step (c) comprises distributing the light with a beam splitter located at a tip of the conduit.
13. The method of claim 11 wherein step (c) comprises reflecting the light with a prism-like mirror located in the conduit.