1. A method of compacting test response data from a circuit, the method comprising:
receiving test response values from a plurality of scan chains and from different scan-shift cycles within a scan chain;
combining the test response values using a plurality of sub-arrays of logic gates thereby directly generating a plurality of output values at a plurality of external outputs, the number of external outputs being less than the number of scan chains, and the sub-arrays of logic gates arranged so as to minimize masking of errors in the test response data.
2. The method of claim 1 wherein the logic gates are XOR gates.
3. The method of claim 1 wherein the test response values in a scan chain are stored in one or more memory elements, thereby providing the plurality of sub-arrays of logic gates with access to test response values from different scan-shift cycles within a scan chain.
4. The method of claim 1 wherein each sub-array can be represented as a Z\xd7C matrix, where Z is the number of external outputs and C is a number of different scan-shift cycles within a scan chain used.
5. The method of claim 4 wherein the matrix representing a sub-array has a same number of logic gates in each column of the matrix and wherein no two matrices are identical.
6. The method of claim 4 wherein there are a fixed number of logic gates within each sub-array and no sub-array is represented by a matrix which is a horizontally-shifted version of another sub-array’s matrix.
7. The method of claim 1 wherein the sub-arrays of logic gates are grouped into a plurality of segments such that control signals can be used to block a segment from being combined to one of the plurality of external outputs, the control signals selected so as to minimize masking by unknown values.
8. A logic testing architecture comprising:
a plurality of scan chains;
a plurality of external outputs, the number of external outputs being less than the number of scan chains;
a plurality of sub-arrays of logic gates, each sub-array coupled to a scan chain, the logic gates in a sub-array arranged so as to propagate and combine test response values from different scan-shift cycles within the plurality of scan chains to directly generate output values at each of the external outputs.
9. The logic testing architecture of claim 8 wherein the logic gates are XOR gates.
10. The logic testing architecture of claim 8 wherein each sub-array further comprises one or more memory elements storing test response values from different scan-shift cycles within a scan chain.
11. The logic testing architecture of claim 8 wherein each sub-array can be represented as a Z\xd7C matrix, where Z is the number of external outputs and C is a number of different scan-shift cycles within a scan chain used.
12. The logic testing architecture of claim 11 wherein the matrix representing a sub-array has a same number of logic gates in each column of the matrix and wherein no two matrices are identical.
13. The logic testing architecture of claim 11 wherein there are a fixed number of logic gates within each sub-array and no sub-array is represented by a matrix which is a horizontally-shifted version of another sub-array’s matrix.
14. The logic testing architecture of claim 8 wherein the sub-arrays of logic gates are grouped into a plurality of segments such that control signals can be used to block a segment from being combined to one of the plurality of external outputs, the control signals selected so as to minimize masking by unknown values.
15. A logic testing architecture comprising:
a plurality of scan chains;
a plurality of external outputs, the number of external outputs being less than the number of scan chains;
a plurality of logic gates coupling the scan chains to the external outputs, the plurality of logic gates arranged as a time-folding matrix which couples unique sets of external outputs to each scan chain.
16. The logic testing architecture of claim 15 wherein the logic gates are XOR gates.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for communicating with a device, the method comprising:
determining, with one or more processors associated with one or more computer systems, a set of calls for an interface associated with a device based on a first XML event received from an application;
receiving, at the one or more computer systems, data in response to invoking the set of determined calls to control the device;
generating, with the one or more processors associated with the one or more computer systems, a second XML event based on the data and an examination of at least one of a time interval or value condition; and
communicating, with the one or more processors associated with the one or more computer systems, the second XML event to the application.
2. The method of claim 1 wherein determining the set of calls for the interface comprises translating the first XML event into one or more calls in the set of calls.
3. The method of claim 1 further comprising:
receiving a data subscription from the application; and
examining the at least one of a time interval or value condition based on the data subscription.
4. The method of claim 1 wherein:
receiving the data in response to invoking the set of determined calls to control the device comprises receiving data for each call in a plurality of calls in the set of calls; and
generating the second XML event comprises aggregating the data for each call in the plurality of calls.
5. The method of claim 1 wherein the first XML event defines a plurality of times; and
wherein receiving the data in response to invoking the set of determined calls to control the device comprises controlling the device at each of the plurality of times.
6. The method of claim 5 wherein controlling the device comprises reading data from the device.
7. The method of claim 5 wherein controlling the device comprises writing data to the device.
8. A data processing system comprising:
an interface associated with a device;
a processor; and
a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor cause the processor to:
determine a set of calls for the interface based on a first XML event received from an application;
receive data in response to invoking the set of determined calls to control the device;
generate a second XML event based on the data and an examination of at least one of a time interval or value condition; and
communicate the second XML event to the application.
9. The system of claim 8 wherein the processor is caused to translate the first XML event into one or more calls in the set of calls.
10. The system of claim 8 wherein the processor is further caused to:
receive a data subscription from the application; and
examine the at least one of a time interval or value condition based on the data subscription.
11. The system of claim 8 wherein the processor is further caused to:
receive the data in response to invoking the set of determined calls to control the device by receiving data for each call in a plurality of calls in the set of determined calls to control the device; and
generate the second XML event by aggregating the data for each call in the plurality of calls.
12. The system of claim 8 wherein the second XML event defines a plurality of times; and
wherein the processor is cause to receive the data in response to invoking the set of determined calls to control the device by controlling the device at each of the plurality of times.
13. The system of claim 8 wherein the processor is caused to receive the first XML event using a web services protocol.
14. The system of claim 8 wherein the processor is caused to receive the first XML event using the hypertext transport protocol (HTTP).
15. A non-transitory computer readable storage medium configured to store a set of code modules which when executed by one or more processors of a computer system cause the processors to communicate with a device, the computer readable medium comprising:
code for determining a set of calls for an interface associated with a device based on a first XML event received from an application;
code for receiving data in response to invoking the set of determined calls to control the device;
code for generating a second XML event based on the data and an examination of at least one of a time interval or value condition; and
code for communicating the second XML event to the application.
16. The non-transitory computer readable storage medium of claim 15 wherein the code for determining the set of calls for the interface comprises code for translating the first XML event into one or more calls in the set of calls.
17. The non-transitory computer readable storage medium of claim 15 further comprising:
code for receiving a data subscription from the application;
code for examining the at least one of a time interval or value condition based on the data subscription.
18. The non-transitory computer readable storage medium of claim 15 wherein:
the code for receiving the data in response to invoking the set of determined calls to control the device comprises code for receiving data for each call in plurality of calls; and
the code for generating the second XML event comprises code for aggregating the data for each call in the plurality of calls.
19. The non-transitory computer readable storage medium of claim 15 wherein the second XML event defines a plurality of times; and
wherein the code for receiving the data in response to invoking the set of determined calls to control the device comprises code for controlling the device at each of the plurality of times.
20. The non-transitory computer readable storage medium of claim 19 wherein the code for controlling the device comprises code for reading data from the device or writing data to the device.