1. A cache memory system, comprising:
an associative cache including a plurality of memory locations to store data and addresses associated with the data;
a first controller that controls access to the plurality of memory locations by a first device;
a second controller that operates independently of the first controller and controls access to the plurality of memory locations by a second device;
an address input for selecting memory locations to be accessed;
at least one first multiplexer that selects addresses to be provided to the address input from among addresses provided by the first device and addresses provided by the second controller;
an address output for outputting addresses retrieved from memory locations along with data associated therewith; and
at least one second multiplexer that selects external addresses to be inputted to the second device from among the addresses outputted at the address output and external addresses provided by the second controller.
2. The system of claim 1, wherein the second controller comprises a data transfer engine that transfers data from a lower-level memory to the memory locations.
3. The system of claim 2, wherein the data transfer engine transfers data from the memory locations to the lower-level memory.
4. The system of claim 3, wherein the data transfer engine comprises a DMA controller.
5. The system of claim 2, wherein the data transfer engine comprises a DMA controller.
6. The system of claim 5, in combination with the first device, wherein the first device comprises a digital signal processor.
7. The system of claim 1, wherein the second controller comprises a DMA controller which provides at least one first address identifying at least one memory location of the second device from which data sets are to be transferred, and at least one second address identifying at least one memory location of the cache to which the data sets are to be transferred.
8. The system of claim 7, wherein the DMA controller is configured such that the second address can be incremented or decremented between consecutively transferred data sets without also incrementing or decrementing the first address between the consecutively transferred data sets.
9. The system of claim 7, wherein the DMA controller is configured such that the second address can be incremented or decremented between consecutively transferred data sets by a different amount than the first address is incremented or decremented between the consecutively transferred data sets.
10. The system of claim 1, wherein the first and second controllers are integrated on a common semiconductor die.
11. The system of claim 1, wherein each of the plurality of memory locations has only a single word line associated therewith.
12. The system of claim 1, further comprising a third controller that controls arbitration for shared cache resources among the first controller and the second controller.
13. The system of claim 1, in combination with the first device, wherein the first device comprises a processor.
14. The combination of claim 13, wherein the processor comprises a digital signal processor.
15. A method, comprising:
selecting addresses to be provided to an address input of an associative cache from among addresses provided by a first device and addresses provided by a second device;
accessing memory locations within the associative cache based upon the selected addresses provided to the address input of the cache;
outputting addresses retrieved from memory locations of the associative cache along with data associated therewith; and
selecting external addresses to be outputted to the second device from among the addresses output from the associative cache and external addresses inputted by the second device.
16. The method of claim 15, wherein accessing memory locations includes using a data transfer engine to transfer data from a lower-level memory to the memory locations of the associative cache.
17. The method of claim 16, wherein accessing memory locations includes using the data transfer engine to transfer data from the memory locations of the associative cache to the lower-level memory.
18. The method of claim 15, wherein each of the memory locations has only a single word line associated therewith.
19. The method of claim 15, wherein accessing memory locations includes using a DMA controller to transfer data from a lower-level memory to memory locations of the associative cache, the DMA controller providing at least one first address identifying at least one memory location of the lower-level memory from which data sets are to be transferred, and further providing at least one second address identifying at least one of the plurality of memory locations to which the data sets are to be transferred.
20. The method of claim 19, wherein accessing memory locations further includes incrementing or decrementing the second address between consecutively transferred data sets without also incrementing or decrementing the first address between the consecutively transferred data sets.
21. The method of claim 19, wherein accessing memory locations further includes incrementing or decrementing the second address between consecutively transferred data sets by a different amount than the first address is incremented or decremented between the consecutively transferred data sets.
22. A cache memory system, comprising:
an associative cache including a plurality of memory locations to store data and addresses associated with the data;
means for selecting addresses to be provided to an address input of an associative cache from among addresses provided by a first device and addresses provided by a second device;
means for accessing locations within the associative cache based upon the selected addresses provided to the address input of the associative cache;
means for outputting addresses retrieved from memory locations of the associative cache along with data associated therewith; and
means for selecting external addresses to be inputted to the second device from among the addresses output from the associative cache and external addresses outputted by a second device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1-14. (canceled)
15. A method of forming a semiconductor device structure comprising:
providing a semiconductor substrate having a major surface;
forming a first region comprising pillars of first and second conductivity type doped material extending in a generally vertical orientation with respect to the major surface, wherein the first conductivity type is opposite to the second conductivity type, and wherein the first pillar is configured as a vertical current path;
forming a second region of the first conductivity type spaced apart from the major surface, wherein the second region adjoins a lower portion of the first region;
forming a third region of the second conductivity type, wherein the third region adjoins the first region between the major surface and the second region;
forming a body region overlying a portion of the third region;
forming a source region formed the body region; and
forming a control electrode adjacent the body region and the source region, wherein the control electrode is configured to control a channel region within the body region but not within the third region.
16. The method of claim 15 further comprising forming a linking region of the first conductivity type, wherein the linking region is between the body region and the third region.
17. The method of claim 15, wherein forming the third region includes forming the third region having a dopant concentration less than or equal to about 5.0\xd71015 atomscm3.
18. The method of claim 15, wherein forming the third region includes forming the third region having a dopant concentration between about 1.0\xd71015 atomscm3 to about 3.0\xd71015 atomscm3.
19. The method of claim 15, wherein forming the first region includes forming the pillar of the first conductivity type adjoining the second and third regions.
20. The method of claim 15, wherein forming the third region includes forming the third region having a thickness from about five microns to about fifteen microns.
21. The method of claim 15 further comprising forming a conductive layer electrically connected to the source region and the third region.
22. The method of claim 15, wherein forming the control electrode comprises forming a trench control electrode, and wherein forming the third region comprises forming the third region overlapping the trench control electrode such that the trench control electrode terminates within the third region.
23. A method of forming a semiconductor device structure comprising:
providing a semiconductor substrate having a major surface;
forming a first region comprising a first pillar of a first conductivity type doped material extending in a generally vertical orientation with respect to the major surface, wherein the first pillar is configured as a vertical current path;
forming a second region of the first conductivity type spaced apart from the major surface, wherein the second region adjoins a lower portion of the first region;
forming a third region of a second conductivity type opposite to the first conductivity type, wherein the third region adjoins the first region between the major surface and the second region;
forming a body region overlying a portion of the third region;
forming a source region formed the body region; and
forming a control electrode adjacent the body region and the source region, wherein the control electrode is configured to control a channel region in the body region, and wherein the control electrode terminates within the third region.
24. The method of claim 23, wherein forming the first region further comprises forming a second pillar of the second conductivity type adjacent the first pillar and extending in a generally vertical orientation with respect to the major surface.
25. The method of claim 24, wherein forming the third region comprises forming the third region having a dopant concentration in a range from about 1.0\xd71015 atomscm3 to about 4.0\xd71015 atomscm3, and wherein the first region has a charge balance other than zero.
26. The method of claim 23 further comprises forming a fourth region of the first conductivity type between the body region and the third region and configured to link a drain end of the channel region to the first pillar
27. A method for forming a semiconductor device comprising:
providing a substrate having a semiconductor layer overlying the substrate, wherein the semiconductor layer has a major surface spaced apart from the substrate;
forming a vertically-oriented doped structure comprising a first pillar of a first conductivity type adjacent to the major surface and extending towards the substrate;
forming a body region of a second conductivity type adjacent to another portion of the major surface;
forming a first horizontally-oriented doped region of the first conductivity type spaced apart from the major surface and between the body region and the substrate, wherein the first horizontally-oriented doped region adjoins the first pillar;
forming a second horizontally-oriented doped region of the second conductivity type spaced apart from the major surface and between the first horizontally-oriented doped region and the substrate; and
forming a gate electrode electrically insulated from the body region and the first horizontally-oriented doped region,
wherein:
a transistor structure of the semiconductor device comprises the first horizontally-oriented doped region, the body region, and the gate electrode; and
the first pillar electrically connects the transistor structure and the substrate to each other.
28. The method of claim 27, wherein forming the second horizontally-oriented doped region comprises forming the second horizontally-oriented doped region having a dopant concentration less than or equal to about 5.0\xd71015 atomscm3.
29. The method of claim 27, wherein forming the second horizontally-oriented doped region comprises forming the second horizontally-oriented doped region having a dopant concentration between about 1.0\xd71015 atomscm3 to about 3.0\xd71015 atomscm3.
30. The method of claim 27, wherein forming the second horizontally-oriented doped region comprises forming the second horizontally-oriented doped region having a thickness from about five microns to about fifteen microns.
31. The method of claim 27, wherein forming the gate electrode comprises forming a trench gate electrode.
32. The method of claim 27 wherein forming the vertically-oriented doped structure comprises forming a second conductive pillar of the second conductivity type adjacent the first pillar and extending towards the substrate.
33. The method of claim 32, wherein forming the vertically-oriented doped structure comprises forming the vertically-oriented doped structure having charge balance other than zero.
34. The method of claim 27 further comprising:
forming a source region in the body region; and
forming a conductive layer electrically coupled to the source region and the second horizontally-oriented doped region.