1. A buck-boost DC-DC converter configured to operate in both a buck mode and a boost mode, and comprising:
converter control circuitry configured to provide a buck mode timing signal and a boost mode timing signal;
converter switching circuitry configured to provide a switching output signal, wherein:
during the buck mode, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal;
during the boost mode, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal; and
a first inductive element is configured to receive and filter the switching output signal to provide a converter output signal.
2. The buck-boost DC-DC converter of claim 1 further comprising a first capacitive element, wherein the first inductive element and the first capacitive element are coupled in series between the converter switching circuitry and ground to form a lowpass filter.
3. The buck-boost DC-DC converter of claim 1 wherein a DC power source is configured to provide a DC source signal to the converter control circuitry and the converter switching circuitry.
4. The buck-boost DC-DC converter of claim 3 wherein the converter control circuitry is further configured to select the one of the buck mode and the boost mode based on a DC source voltage of the DC source signal and a setpoint of a converter output voltage of the converter output signal.
5. The buck-boost DC-DC converter of claim 1 wherein the converter control circuitry is further configured to select the buck mode when a setpoint of a converter output voltage of the converter output signal is less than a DC source voltage, and select the boost mode when the setpoint of the converter output voltage is greater than the DC source voltage.
6. The buck-boost DC-DC converter of claim 1 wherein during the buck mode, when the buck pulse-width of the switching output signal is greater than the buck pulse-width threshold, the buck pulse-width is not limited based on the boost mode timing signal; and during the boost mode, when the boost pulse-width of the switching output signal is greater than the boost pulse-width threshold, the boost pulse-width is not limited based on the buck mode timing signal.
7. The buck-boost DC-DC converter of claim 1 wherein during the buck mode, the switching output signal toggles between being based on ground and being based on a DC source signal, such that a switching output voltage of the switching output signal toggles between nominally zero volts and nominally a DC source voltage of the DC source signal.
8. The buck-boost DC-DC converter of claim 1 further comprising a boost mode power supply configured to provide a boost supply signal having a boost supply voltage.
9. The buck-boost DC-DC converter of claim 8 wherein the boost mode power supply comprises a capacitor-based charge pump.
10. The buck-boost DC-DC converter of claim 8 wherein during the buck mode, the switching output signal toggles between being based on the boost supply signal and being based on ground, such that the boost supply voltage is nominally equal to a DC source voltage of a DC source signal. As such, a switching output voltage of the switching output signal toggles between nominally zero volts and nominally the DC source voltage.
11. The buck-boost DC-DC converter of claim 8 wherein during the boost mode, the switching output signal toggles between being based on the boost supply signal and being based on a DC source signal, such that the boost supply voltage is nominally equal to 1.5 times a DC source voltage of the DC source signal, wherein a switching output voltage of the switching output signal toggles between nominally the DC source voltage and nominally 1.5 times the DC source voltage.
12. The buck-boost DC-DC converter of claim 8 wherein during the boost mode, the switching output signal toggles between being based on the boost supply signal and being based on a DC source signal, such that the boost supply voltage is nominally equal to 2 times a DC source voltage of the DC source signal, wherein a switching output voltage of the switching output signal toggles between nominally the DC source voltage and nominally 2 times the DC source voltage.
13. The buck-boost DC-DC converter of claim 1 wherein a linear amplifier is configured to at least partially provide an envelope power supply signal to a radio frequency (RF) power amplifier (PA) using the converter output signal.
14. The buck-boost DC-DC converter of claim 13 wherein the linear amplifier is further configured to regulate a voltage of the envelope power supply signal based on a setpoint of the envelope power supply signal.
15. The buck-boost DC-DC converter of claim 14 wherein the envelope power supply signal is amplitude modulated to provide at least partial envelope tracking of an RF transmit signal from the RF PA.
16. The buck-boost DC-DC converter of claim 15 wherein a bandwidth of the envelope power supply signal is greater than 10 megahertz.
17. The buck-boost DC-DC converter of claim 13 wherein a switching supply is configured to at least partially provide the envelope power supply signal.
18. The buck-boost DC-DC converter of claim 13 wherein the RF PA is configured to receive and amplify an RF input signal to provide an RF transmit signal using the envelope power supply signal, which provides power for amplification.
19. The buck-boost DC-DC converter of claim 13 wherein the converter output signal is based on a maximum amplitude of the envelope power supply signal.
20. A method comprising:
operating a buck-boost DC-DC converter in both a buck mode and a boost mode;
providing a buck mode timing signal, a boost mode timing signal, and a switching output signal, wherein:
during the buck mode, when a buck pulse-width of the switching output signal is less than a buck pulse-width threshold, the buck pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal; and
during the boost mode, when a boost pulse-width of the switching output signal is less than a boost pulse-width threshold, the boost pulse-width is limited based on both the buck mode timing signal and the boost mode timing signal; and
receiving and filtering the switching output signal to provide a converter output signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A process tube for fabrication of semiconductor devices, comprising:
a plurality of process gas injection slits for supplying process gas, each of the process gas injection slits being formed on an interior surface of each of a plurality of parallel recesses, each recess being in the shape of an elongated narrow depression on an inner surface of a first side of a cylindrical tube body; and
a plurality of waste gas exhaust apertures for evacuating waste gas, the waste gas exhaust apertures being formed on a second side of the cylindrical tube body inner surface opposite the first side.
2. The process tube of claim 1, wherein the tube body comprises:
a buffer gas pipe provided as a space formed within the first side along a circumference of the cylindrical tube body, the buffer gas pipe communicating with the process gas injection slits; and
a gas exhaust pipe provided as a space formed within the second side along the circumference, the gas exhaust pipe communicating with the waste gas exhaust apertures.
3. The process tube of claim 2, wherein the buffer gas pipe is connected to a gas injection pipe, which is provided in the tube body, through a plurality of passages.
4. The process tube of claim 3, wherein the gas injection pipe is connected to a gas control system pipe.
5. The process tube of claim 2, wherein the gas exhaust pipe is connected to a vacuum pump pipe.
6. The process tube of claim 1, wherein a top of the cylindrical tube body is closed.
7. The process tube of claim 1, wherein at least one process gas injection slit is formed on the first side of the tube body within an angle of 160 degrees in the circumferential direction.
8. The process tube of claim 1, wherein at least one waste gas exhaust aperture is formed on the second side of the tube body within an angle of 160 degrees in the circumferential direction.
9. The process tube of claim 7, wherein each process gas injection slit includes multiple slits formed at a center, left and right portion of the inner surface of each recess.
10. The precess tube of claim 8, wherein the waste gas exhaust apertures are provided on the second side spaced apart by predetermined distances in order to prevent turbulence.
11. A semiconductor device fabrication apparatus comprising:
a process tube comprising a plurality of process gas injection slits for supplying process gas, each of the process gas injection slits being formed on an interior surface of each of a plurality of parallel recesses, each recess being in the shape of an elongated narrow depression on an inner surface of a first side of a cylindrical tube body; and a plurality of waste gas exhaust apertures for evacuating waste gas, the waste gas exhaust apertures being formed on a second side of the cylindrical tube body inner surface opposite the first side.
a heating chamber for applying external heat to the process tube;
a gas control system pipe for supplying gas to the process gas injection slits of the process tube;
a vacuum pump pipe connected to the waste gas exhaust apertures of the process tube; and
a boat movable in and out of the process tube.
12. The apparatus of claim 11, wherein the boat is for low pressure chemical vapor deposition equipment or oxidationdiffusion equipment.
13. The apparatus of claim 11, wherein the boat rotates at a rate of 1-70 rpmmin during the deposition of a film.
14. The apparatus of claim 11, wherein the boat comprises quartz plates on which wafers are mounted, and the pitch between quartz plates is in the range of 3.5-15 mm.
15. The apparatus of claim 11, wherein the gas control system pipe is connected to the process gas injection slits through a gas injection pipe and a buffer gas exhaust pipe, which are formed in the process tube, and wherein the pressure in the buffer gas exhaust pipe is 1-40 torr.
16. The apparatus of claim 11, wherein the process gas injection slits are formed in an inner surface of each recess in the first side of the process tube within an angle of 160 degrees in the circumferential direction.
17. The apparatus of claim 11, wherein the waste gas injection apertures are formed on the inner surface of the second side of the process tube within an angle of 160 degrees in the circumferential direction.
18. The apparatus of claim 11, wherein at least one process gas injection slit is formed on the bottom of each recess of the process tube.
19. The apparatus of claim 11, wherein each process gas injection slit includes multiple slits formed at a center, left and right portion of the inner surface of each recess.
20. The apparatus of claim 11, wherein the waste gas exhaust apertures are provided on the second side spaced apart by predetermined distances in order to prevent turbulence.