1. In a communication system transmitting data in one frequency band using at least two orthogonal subcarriers, a method of modulation, comprising the steps of:
adding information bits indicating an amplitude reference and a phase reference to an input bit sequence by a specific time interval unit; and
carrying out differential amplitude phase shift keying (DAPSK) on the input bit sequence using the amplitude and phase references.
2. The method of claim 1, further comprising the step of re-ordering symbols differentially modulated using the amplitude reference and phase reference so that the symbols can be transmitted via subcarriers corresponding to mutually adjacent frequencies.
3. The method of claim 1, wherein subcarriers not transmitting the data are located at both ends of the frequency band in a frequency domain.
4. The method of claim 1, wherein the specific time interval is an orthogonal frequency division multiplexing (OFDM) block.
5. The method of claim 1, wherein the differential amplitude phase shift keying is 16-ary DPASK modulation.
6. A method of modulation, which is applied to a broadcast using orthogonal frequency division multiplexing (OFDM), the method comprising the steps of:
inserting one pilot tone in each orthogonal frequency division multiplexing block; and
carrying out differential amplitude phase shift keying (DAPSK) using pilot tone as a reference.
7. The method of claim 6, further comprising the steps of inserting guard tones not transmitting data in both ends of a band for broadcast in a frequency domain.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A data processor receiving data from a memory being capable of storing N (2) words of data at each address and processing the data;
said data processor comprising:
M (1) registers each being capable of holding one of said addresses and N words of data;
a selector for selecting and outputting N consecutive words of data specified on a word-by-word basis from among data held in said M registers and data read from said memory; and
a controller for, when said N consecutive words of data have a portion which is not held in any of said M registers, reading out N words of data containing said portion from said memory and, when said M registers include a no-data-holding register which does not hold any of said N consecutive words of data, updating values of said no-data-holding register with N words of data read from said memory and its address.
2. The data processor according to claim 1, wherein
said M registers include two or more registers.
3. The data processor according to claim 1, wherein
said controller writes N words of data into said memory at a specified address in response to a write instruction and disables all of said M registers so that said M registers are equivalent to those which do not hold any address and data in said memory.
4. The data processor according to claim 1, wherein
said controller writes N words of data into said memory at a specified address in response to a write instruction and, when said M registers include a register holding said specified address, updates N words of data held in that register with said N words of data written into said memory.
5. The data processor according to claim 1, wherein
said controller reads out N words of data which is stored at a specified address in said memory, in response to an aligned-data read instruction; and
said selector outputs said N words of data read from said memory in response to said aligned-data read instruction.
6. The data processor according to claim 1, wherein
said controller reads out N words of data containing a specified word from said memory, in response to a single-word parallel read instruction; and
said selector outputs N words in parallel, each word being said specified word included in said N words of data read from said memory, in response to said single-word parallel read instruction.
7. The data processor according to claim 1, wherein
said controller includes another register and, when updating a value of either of said M registers, computes an address contiguous to the one to be held in the updated register and loads the computed address into said another register.
8. The data processor according to claim 1, further receiving data from another memory capable of storing N (2) words of data at each address, said data processor further comprising:
other M(1) registers each being capable of holding one of said addresses of said another memory and N words of data;
another selector for selecting and outputting other N consecutive words of data specified on a word-by-word basis from among data held in said other M registers and data read from said another memory;
another controller for, when said other N consecutive words of data have another portion which is not held in any of said other M registers, reading out N words of data containing said another portion from said another data memory and, when said other M registers include a no-data-holding register which does not hold any of said other N consecutive words of data, updating values of said no-data-holding register with said N words of data read from said another memory and its address; and
an operation unit for performing an arithmetic or logic operation using both data output from said selector and said another selector.
9. A data processor receiving data from a memory being capable of storing N (2) words of data at each address and processing said data;
said data processor comprising:
a controller for reading out N words of data which is stored at an address containing a specified word from said memory; and
a selector for outputting N words in parallel, each word being said specified word included in said N words of data read from said memory.