1. A system for decoding a data symbol marked on an object, the system comprising a wafer identification fault server configured to:
receive a digital image, the digital image comprising an image of a data symbol marked on an object, the data symbol comprising a message encoded in a set of data cells arranged in a regular pattern, each data cell comprising one bit of information encoded using a recognizable mark at a location of the data cell;
process the digital image to form a set of classified data cells, wherein one or more classified data cells from the set of classified data cells comprises an error, each classified data cell being associated with a data cell from the set of data cells, and comprising:
a data cell location of the associated data cell in the digital image; and
a data cell state indicating a presence of a recognizable mark of the associated data cell in the digital image;
transmit user interface data comprising the digital image and interactive graphics, the interactive graphics including at least one data cell control, each data cell control being associated with a classified data cell in the set of classified data cells;
receive interaction data from the interactive graphics that modifies a data cell location, a data cell state, or both, of at least one classified data cell from the set of classified data cells to form a modified set of classified data cells; and
generate an error free decoded message string based on the modified set of classified data cells.
2. The system of claim 1, wherein the system is further configured to:
generate an error free data string based on the modified set of classified data cells, wherein the error free data string comprises one or more characters and a checksum for each of the one or more characters; and
generate the error free decoded message string based on the error free data string.
3. The system of claim 1, further comprising a display in communication with the computing device configured to:
receive the user interface data and display the user interface data; and
display the error free decoded message string.
4. The system of claim 1, wherein the computing device is further configured to:
generate an error-containing decoded message string based on the set of classified data cells; and
transmit second display data that includes a character control comprising a character of the error-containing decoded message string.
5. The system of claim 4, wherein the computing device is further configured to:
receive second interaction data from the character control to change the character to a different character; and
modify a binary classification of one or more classified data cells based on the second interaction data to reflect the different character.
6. The system of claim 4, wherein the computing device is further configured to:
receive second interaction data from the character control to identify one or more data cell controls associated with the character; and
transmit third display data that includes graphical identification data for the one or more cell controls associated with the character.
7. The system of claim 1, wherein the computing device is further configured to receive a set of digital images of the object, each image being captured using a predefined set of lighting and exposure settings.
8. The system of claim 7, wherein the computing device is further configured to:
display an interactive graphical control configured to allow selection of an image from the set of digital images for display;
receive selection data indicative of a selected image from the set of digital images for display; and
transmit second user interface data comprising the selected image.
9. The system of claim 8, wherein the computing device is further configured to:
generate second interactive graphics based on the selected image; and
transmit third user interface data comprising the second interactive graphics.
10. The system of claim 7, wherein the computing device is further configured to generate a composite digital image based on the set of digital images.
11. The system of claim 1, wherein:
the object comprising the data symbol is a silicon wafer, and recognizable marks of the data symbol are formed on a surface of the wafer by laser etching; and
wherein the regular pattern comprises a grid structure, wherein each recognizable mark comprises a marking on a vertex of the grid structure.
12. The system of claim 1, wherein the computing device is further configured to:
receive the digital image that has not been automatically decoded from one or more image capturing devices.
13. The system of claim 1, wherein the interaction data changes:
a binary classification of a classified data cell from false to true or from true to false, in either case to indicate that the system incorrectly classified an associated data cell of the data symbol.
14. The system of claim 1, wherein the computing device is further configured to:
generate display information for each data cell control based on a data cell location of the associated classified data cell, by calculating a position for each data cell control by rotating, scaling, translating, or any combination thereof, the data cell location of the associated classified data cell.
15. A computerized method for data symbol recognition, comprising:
receiving, by a wafer identification fault server, a digital image, the digital image comprising an image of a data symbol marked on an object, the data symbol comprising a message encoded in a set of data cells arranged in a regular pattern, each data cell comprising one bit of information encoded using a recognizable mark at a location of the data cell;
processing, by the wafer identification fault server, the digital image to form a set of classified data cells, wherein one or more classified data cells from the set of classified data cells comprises an error, each classified data cell being associated with a data cell from the set of data cells, and comprising:
a data cell location of the associated data cell in the digital image; and
a data cell state indicating a presence of a recognizable mark of the associated data cell in the digital image;
transmitting, by the wafer identification fault server, user interface data comprising the digital image overlaid with interactive graphics, the interactive graphics including at least one data cell control, each data cell control being associated with a classified data cell in the set of classified data cells;
receiving, by the wafer identification fault server, interaction data from the interactive graphics that modifies a data cell location, a data cell state, or both, of at least one classified data cell from the set of classified data cells to form a modified set of classified data cells; and
generating, by the wafer identification fault server, an error free decoded message string based on the modified set of classified data cells.
16. The method of claim 15, further comprising:
generating an error free data string based on the modified set of classified data cells, wherein the error free data string comprises one or more characters and a checksum for each of the one or more characters; and
generating the error free decoded message string based on the error free data string.
17. The method of claim 15, further comprising:
generating an error-containing decoded message string based on the set of classified data cells; and
transmitting second display data that includes a character control comprising a character of the error-containing decoded message string.
18. The method of claim 17, further comprising:
receiving second interaction data from the character control to change the character to a different character; and
modifying a binary classification of one or more classified data cells based on the second interaction data to reflect the different character.
19. The method of claim 17, further comprising:
receiving second interaction data from the character control to identify one or more data cell controls associated with the character; and
transmitting third display data that includes graphical identification data for the one or more cell controls associated with the character.
20. A computer program product, tangibly embodied in a non-transitory computer readable medium, the computer program product including instructions being configured to cause a data processing apparatus to:
receive a digital image, the digital image comprising an image of a data symbol marked on an object, the data symbol comprising a message encoded in a set of data cells arranged in a regular pattern, each data cell comprising one bit of information encoded using a recognizable mark at a location of the data cell;
process the digital image to form a set of classified data cells, wherein one or more classified data cells from the set of classified data cells comprises an error, each classified data cell being associated with a data cell from the set of data cells, and comprising:
a data cell location of the associated data cell in the digital image; and
a data cell state indicating a presence of a recognizable mark of the associated data cell in the digital image;
transmit user interface data comprising the digital image overlaid with interactive graphics, the interactive graphics including at least one data cell control, each data cell control being associated with a classified data cell in the set of classified data cells;
receive interaction data from the interactive graphics that modifies a data cell location, a data cell state, or both, of at least one classified data cell from the set of classified data cells to form a modified set of classified data cells; and
generate an error free decoded message string based on the modified set of classified data cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing a semiconductor package, comprising the steps of:
forming a strip substrate including:
a plurality of unit substrates, each being provided with a first connection pad and a second connection pad on a first surface of the unit substrate and each unit substrate being electrically and physically isolated from each other with the intervention of saw lines,
first ground connection pads formed on the respective unit substrates, each of the first ground connection pads being electrically coupled with the first connection pad,
second ground connection pads formed on the saw line and electrically isolated from the unit substrates, and
test wiring formed on the saw line, the test wiring being electrically isolated from the unit substrates and electrically coupled with the second ground connection pads; and
attaching semiconductor chips onto the respective unit substrates;
forming first conductive wires that electrically connect the first ground connection pads and the second ground connection pads;
forming second conductive wires that electrically connect the first connection pads of the unit substrates and the first bonding pads of the semiconductor chips; and
forming third conductive wires that electrically connect the second connection pads of the unit substrates and the second bonding pads of the semiconductor chips.
2. The method of claim 1, further comprising, after forming the strip substrate and before attaching the semiconductor chips onto the respective unit substrates, the step of:
testing for an electric fault of conductive via formed in an inside of the unit substrate with the use of the unit substrate.
3. The method of claim 2, wherein the testing of electric faults of the conductive via is implemented in a manner of flowing currents to circuit wirings of the respective unit substrates and monitoring whether the currents flow between circuit wirings formed on the first surface of the unit substrate and circuit wirings formed on a second surface of the unit substrate.
4. The method of claim 3, wherein attaching semiconductor chips onto the respective unit substrates is implemented by attaching the semiconductor chip onto the unit substrate that has passed the electrical fault test on the conductive via, and not attaching the semiconductor chip onto the unit substrate that has failed the electrical fault test.
5. The method of claim 1, wherein forming the third conductive wire includes the steps of:
bonding one end of the conductive wire onto the second bonding pad;
bonding the other portion of the conductive wire onto the second connection pad; and
cutting the conductive wire.
6. The method of claim 5, further comprising, after bonding the one end of the conductive wire onto the second bonding pad and before bonding the other portion of the conductive wire onto the second connection pad, the step of:
monitoring a bonding status between the conductive wire and the second bonding pad through the test wiring by applying a current through the conductive wire.
7. The method of claim 5, further comprising, after bonding the other portion of the conductive wire onto the second connection pad and before cutting the conductive wire, the step of:
monitoring a bonding status between the conductive wire and the second connection pad through the test wiring by applying a current through the conductive wire.
8. The method of claim 5, further comprising, after cutting the conductive wire, the step of:
Monitoring a cutting status of the conductive wire through the test wiring by applying currents through the conductive wire.
9. The method of claim 1, further comprising, after forming the third conductive wires, the steps of:
forming a mold part for molding the first surface including the semiconductor chips and the first, second and third conductive wires; and
cutting the strip substrate, the first conductive wires and the mold part along the saw lines.
10. A semiconductor package, comprising:
a unit substrate formed with first and second connection pads on a first surface thereof;
a first ground connection pad formed on the unit substrate and electrically coupled with the first connection pad;
a semiconductor chip attached onto the first surface of the unit substrate, the semiconductor chip having a first bonding pad electrically coupled with the first connection pad and a second bonding pad electrically coupled with the second connection pad;
a mold part formed over the first surface of the unit substrate and the semiconductor chip;
a first conductive wire having a first end electrically coupled with the first ground connection pad and an electrically opened second end;
a second conductive wire formed in an inside of the mold part and electrically coupling the first connection pad and the first bonding pad; and
a third conductive wire formed in the inside of the mold part and electrically coupling the second connection pad and the second bonding pad.
11. The semiconductor package of claim 10, further comprising:
a wiring for electrically coupling the first connection pad and the first ground connection pad.
12. The semiconductor package of claim 10, wherein the first connection pad and the first ground connection pad are formed integrally.
13. The semiconductor package of claim 10, wherein at least two first ground connection pads are formed over the first surface of the unit substrate.
14. The semiconductor package of claim 13, wherein two or more first ground connection pads are electrically coupled to one first connection pad.
15. The semiconductor package of claim 13, wherein the unit substrate is provided with the first connection pad in plural such that the first connection pads correspond one-to-one to the plurality of the first ground connection pads,
wherein the first ground connection pads are electrically coupled to the corresponding first connection pads, respectively.
16. The semiconductor package of claim 10, wherein the unit substrate includes:
a first circuit wiring layer formed over the first surface and having the first connection pad, the second connection pad and the first ground connection pad;
a second circuit wiring layer formed over the second surface of the unit substrate which is opposite to the first surface;
a third circuit wiring layer formed in an inside of the unit substrate; and
conductive vias for electrically coupling the first circuit wiring layer with the third circuit wiring layer or the second circuit wiring layer with the third circuit wiring layer through the first surface or the second surface.
17. The semiconductor package of claim 10, wherein the first bonding pad is electrically coupled with the second bonding pad through a circuit unit formed in an inside of the semiconductor chip.
18. The semiconductor package of claim 10, wherein the second end of the second conductive wire passes through the mold part to be exposed to the side surface of the mold part.
19. An electronic system including a controller, an interface, an inputoutput unit, and a memory device coupled with one another through a bus, the memory device including a semiconductor package comprising:
a unit substrate formed with first and second connection pads over a first surface thereof;
a first ground connection pad formed over the first surface of the unit substrate and electrically coupled with the first connection pad;
a semiconductor chip attached onto the first surface of the unit substrate, the semiconductor chip having a first bonding pad electrically coupled with the first connection pad and a second bonding pad electrically coupled with the second connection pad;
a mold part formed over the first surface of the unit substrate and the semiconductor chip;
a first conductive wire having a first end electrically coupled with the first ground connection pad and an electrically opened second end;
a second conductive wire formed in an inside of the mold part and electrically coupling the first connection pad and the first bonding pad; and
a third conductive wire formed in the inside of the mold part and electrically coupling the second connection pad and the second bonding pad.