1. A method comprising:
selecting code for evaluation;
representing a code execution path for the selected code as a control flow graph, each node in the flow graph representing a code block;
assigning a user-prioritization adjustment value to the block in the control flow graph, the assigned value based upon a position of the code block within the control flow graph, and the assigned value selected from the group consisting of: de-emphasizing the code block and emphasizing the code block;
calculating a weighted code coverage score for the code block based upon the assigned value and a proximity value defined by a proximity of the code block to a second code block in the flow graph, the second code block having a non-zero assigned value;
defining a weighted code coverage goal for testing the selected code based upon an aggregated weighted code coverage score for the code blocks;
measuring execution for the code blocks during test execution, and aggregating the weighted code coverage scores of the executed code blocks, wherein the defined weighted code coverage goal is met when the aggregated scores of the executed blocks at least meets the defined code coverage goal.
2. The method of claim 1, wherein the code block is a sequence of code instructions consisting of one entry point and one exit point.
3. The system of claim 1, further comprising calculating the proximity value based upon a conditional branch distance for a select block from a neighboring block, wherein the neighboring block has the non-zero value.
4. The method of claim 1, wherein emphasizing a code block includes assigning a high priority adjustment value to a new code block.
5. The method of claim 1, wherein emphasizing a code block includes assigning a high priority adjustment value to a code block historically known to contain an error.
6. The method of claim 1, wherein de-emphasizing a code block includes assigning a low priority adjustment value to a disabled code block.
7. A computer system comprising:
a processor in communication with memory, the memory to select code for evaluation;
a manager in communication with the processor to represent a code execution path for the selected code as a control flow graph, each node in the flow graph representing a code block;
the manager to assign a user-prioritization adjustment value to the block in the control flow graph, the assigned value based upon a position of the code block within the control flow graph, and the assigned value selected from the group consisting of: de-emphasizing the code block and emphasizing the code block;
the manager to calculate a weighted code coverage score for the code block based upon the assigned value and a proximity value defined by a proximity of the code block to a second code block in the flow graph, the second code block having a non-zero assigned value;
the manager to define a weighted code coverage goal for testing the selected code based upon an aggregated weighted code coverage score for the code blocks; and
an evaluator in communication with the manager, the evaluator to:
measure execution for the code blocks during test execution, and aggregate the weighted code coverage scores of the executed code blocks, wherein the defined weighted code coverage goal is met when the aggregated scores of the executed blocks at least meet the defined code coverage goal.
8. The system of claim 7, wherein the code block is a sequence of code instructions consisting of one entry point and one exit point.
9. The system of claim 7, further comprising the manager to calculate the proximity value based upon a conditional branch distance for a select block from a neighboring block, wherein the neighboring block has the non-zero value.
10. The system of claim 7, wherein emphasis of a code block includes assignment of a high priority adjustment value to a new code block.
11. The system of claim 7, wherein emphasis of a code block includes assignment of a high priority adjustment value to a code block historically known to contain an error.
12. The system of claim 7, wherein de-emphasis of a code block includes assignment of a low priority adjustment value to a disabled code block.
13. An article comprising:
a computer readable data storage device including computer instructions configured to select code for error evaluation, the instructions comprising:
instructions to select code for evaluation;
instructions to represent a code execution path for the selected code as a control flow graph, each node in the flow graph representing a code block;
instructions to assign a user-prioritization adjustment value to the block in the control flow graph, the assigned value based upon a position of the code block within the control flow graph, and the assigned value selected from the group consisting of: de-emphasizing the code block and emphasizing the code block;
instructions to calculate a weighted code coverage score for the code block based upon the assigned value and a proximity value defined by a proximity of the code block to a second code block in the flow graph, the second code block having a non-zero assigned value;
instructions to define a weighted code coverage goal for testing the selected code based upon an aggregated weighted code coverage score for the code blocks; and
instructions to measure execution for the code blocks during test execution, and aggregate the weighted code coverage scores of the executed code blocks, wherein the defined weighted code coverage goal is met when the aggregated scores of the executed blocks at least meet the defined code coverage goal.
14. The article of claim 13, wherein the code block is a sequence of code instructions consisting of one entry point and one exit point.
15. The article of claim 13, further comprising instructions to calculate the proximity value based upon a conditional branch distance for a select block from a neighboring block, wherein the neighboring block has the non-zero value.
16. The article of claim 13, wherein emphasizing a code block includes assigning a high priority adjustment value to a new code block.
17. The article of claim 13, wherein emphasizing a code block includes assigning a high priority adjustment value to a code block historically known to contain an error.
18. The article of claim 13, wherein said de-emphasizing a code block includes assigning a low priority adjustment value to a disabled code block.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of providing an efficient FIFO memory comprising:
receiving data having a plurality of portions;
alternately writing said data to a first memory and a second memory; and
alternately reading said data from said first memory and said second memory, wherein alternately reading said data comprises alternately writing said data to a first data register and a second data register and alternately reading said data from said first data register and said second data register,
wherein each of said first memory and said second memory is not concurrently written and read.
2. The method of claim 1, wherein the alternately writing comprises writing a first portion of said data to said first memory and writing a second portion of said data to said second memory.
3. The method of claim 1, wherein the alternately reading comprises writing a first portion of said data from said first memory to a first data register, reading said first portion of said data from said first data register, writing a second portion of said data from said second memory to a second data register, and reading said second portion of said data from said second data register.
4. The method of claim 1, wherein the alternately writing comprises alternating memory after writing each portion of said data.
5. The method of claim 1, wherein the alternately reading comprises alternating memory after reading each portion of said data.
6. The method of claim 1, wherein the alternately reading and the alternately writing are synchronous.
7. Circuitry for providing an efficient FIFO memory comprising:
means for receiving data having a plurality of portions;
means for alternately writing said data to a first memory means and a second memory means; and
means for alternately reading said data from said first memory means and said second memory means, wherein means for alternately reading said data comprises means for alternately writing said data to a first data register means and a second data register means and means for alternately reading said data from said first data register means and said second data register means,
wherein each of said first memory means and said second memory means is not concurrently written and read.
8. The circuitry of claim 7, wherein the means for alternately writing comprises means for writing a first portion of said data to said first memory means and means for writing a second portion of said data to said second memory means.
9. The circuitry of claim 7, wherein the means for alternately reading comprises means for writing a first portion of said data from said first memory means to a first data register means, means for reading said first portion of said data from said first data register means, means for writing a second portion of said data from said second memory means to a second data register means, and means for reading said second portion of said data from said second data register means.
10. The circuitry of claim 7, wherein the means for alternately writing comprises means for alternating memory means after writing each portion of said data.
11. The circuitry of claim 7, wherein the means for alternately reading comprises means for alternating memory means after reading each portion of said data.
12. The circuitry of claim 7, wherein the means for alternately reading and the means for alternately writing are synchronous.
13. FIFO memory comprising:
a first memory bank and a second memory bank;
a first data register and a second data register;
WRITE logic operative to receive data having a plurality of portions and to alternately write said data to said first memory bank and said second memory bank; and
READ logic operative to alternately read said data from said first memory bank and said second memory bank, wherein the READ logic is further operative to alternately write said data to said first data register and said second data register and alternately read said data from said first data register and said second data register,
wherein each of said first memory bank and said second memory bank is not concurrently written and read.
14. The FIFO memory of claim 13, wherein the WRITE logic operative to alternately write said data is further operative to write a first portion of said data to said first memory bank and to write a second portion of said data to said second memory bank.
15. The FIFO memory of claim 13, wherein the READ logic operative to alternately read said data is further operative to write a first portion of said data from said first memory bank to a first data register, to read said first portion of said data from said first data register, to write a second portion of said data from said second memory bank to a second data register, and to read said second portion of said data from said second data register.
16. The FIFO memory of claim 13, wherein the WRITE logic operative to alternately write said data is further operative to alternate memory banks after writing each portion of said data.
17. The FIFO memory of claim 13, wherein the READ logic operative to alternately read said data is further operative to alternate memory banks after reading each portion of said data.
18. The FIFO memory of claim 13, wherein the WRITE logic and READ logic are synchronous.
19. A method of providing an efficient FIFO memory comprising:
receiving data having a plurality of portions;
alternately writing said data to a first memory and to a second memory, wherein at least two consecutive portions of data are written to one of said first memory and said second memory; and
alternately reading said data from said first memory and said second memory,
wherein each of said first memory and said second memory is not concurrently written and read.
20. The method of claim 19, wherein a plurality of consecutive portions of data are written to said first memory and said second memory.
21. The method of claim 19, wherein alternately writing and alternately reading comprise alternating memory in accordance with a predetermined pattern.
22. The method of claim 19, further comprising:
writing a first portion of said data to a data register; and
reading said first portion of said data from said data register.
23. Circuitry for providing an efficient FIFO memory comprising:
means for receiving data having a plurality of portions;
means for alternately writing said data to a first memory means and to a second memory means, wherein at least two consecutive portions of data are written to one of said first memory means and said second memory means; and
means for alternately reading said data from said first memory means and said second memory means,
wherein each of said first memory means and said second memory means is not concurrently written and read.
24. The circuitry of claim 23, wherein a plurality of consecutive portions of data are written to said first memory means and said second memory means.
25. The circuitry of claim 23, wherein alternately writing means and alternately reading means comprise alternating memory means in accordance with a predetermined pattern.
26. The circuitry of claim 23, further comprising:
means for writing a first portion of said data to a data register means; and
means for reading said first portion of said data from said data register means.
27. FIFO memory comprising:
a first memory bank and a second memory bank;
WRITE logic operative to receive data having a plurality of portions and to alternately write said data to said first memory bank and to said second memory bank, wherein at least two consecutive portions of data are written to one of said first memory bank and said second memory bank; and
READ logical operative to alternately read said data from said first memory bank and said second memory bank,
wherein each of said first memory bank and said second memory bank is not concurrently written and read.
28. The FIFO memory of claim 27, wherein a plurality of consecutive portions of data are written to said first memory bank and said second memory bank.
29. The FIFO memory of claim 27, wherein the WRITE logic operative to alternately write said data and the READ logic operative to alternately read said data are further operative to alternate memory banks in accordance with a predetermined pattern.
30. The FIFO memory of claim 27, further comprising:
a data register operative to store a portion of said data; and
READ logic operative to read said first portion of said data from said data register.