1. A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test modes are executed in the chip, and the status of the test modes or test results are output from the chip, the method comprising:
providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers, n and m being natural numbers greater than or equal to 1;
programming the m different register groups by filling the m different register groups with m first bit strings, each bit string being respectively assignable to a state of n test modes;
transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and
using a serial second bit string to read out test results or the status of the test modes.
2. The method of claim 1, wherein the m first bit strings are different in the state of at least one test mode.
3. The method of claim 1, wherein the m register groups are put into a definable initial state by being filled with m first bit strings.
4. The method of claim 1, wherein at least one of the m first bit strings is provided with at least one binary check bit, a check bit in a first logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are skipped until a check bit in a second logic state is detected by the test logic unit, and a check bit in the second logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are not skipped until a check bit in the first logic state is detected by the test logic unit.
5. The method of claim 4, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode.
6. The method of claim 4, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode.
7. The method of claim 4, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode function.
8. The method of claim 4, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode function.
9. The method of claim 4, wherein a check bit is placed in front of at least one bit string.
10. The method of claim 4, wherein a check bit is placed in front of all of the bit sequences that are associated with at least one test mode.
11. The method of claim 4, wherein a check bit is placed in front of all of the bit sequences that are associated with an individual test mode.
12. The method of claim 4, wherein a bit sequence that is associated with a test mode is used to activate and deactivate the test mode.
13. The method of claim 4, wherein a bit sequence that is associated with a test mode or test mode function is used to set parameters of the test mode.
14. The method of claim 1, wherein the second bit string is provided with at least one binary check bit, a check bit in a first logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are skipped until a check bit in a second logic state is detected by the test logic unit, and a check bit in the second logic state being used to control the test logic unit such that those bits in the bit string that follows the check bit are not skipped until a check bit in the first logic state is detected by the test logic unit.
15. The method of claim 14, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode or test mode function.
16. The method of claim 14, wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode or individual test mode function.
17. The method of claim 14, wherein a check bit is placed in front of at least one bit string.
18. The method of claim 14, wherein a check bit is placed in front of all of the bit sequences that are associated with at least one test mode or an individual test mode.
19. The method of claim 14, wherein a bit sequence that is associated with a test mode is used to activate and deactivate the test mode.
20. The method of claim 14, wherein a bit sequence that is associated with a test mode or test mode function is used to set parameters of the test mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of identifying objects in a hierarchical circuit design, comprising:
generating object configuration templates for a hierarchical circuit design, each object configuration template
corresponding to a hierarchical cell in the hierarchical circuit design and
having configuration information describing relationships for objects associated with the corresponding hierarchical cell, the configuration information including instance specific configuration information for different instances of the corresponding hierarchical cell; and
analyzing the configuration information of an object configuration template to determine if an instance of an object associated with the corresponding hierarchical cell matches defined configuration criteria.
2. The method recited in claim 1, further comprising displaying the identified object instances.
3. The method recited in claim 2, further comprising displaying the identified object instances by displaying identification information for the object instances on a display monitor.
4. The method recited in claim 2, further comprising displaying the identified object instances by printing identification information for the object instances onto a written medium.
5. The method recited in claim 1, wherein the objects are circuit devices.
6. The method recited in claim 1, wherein the hierarchical circuit design is a hierarchically organized netlist.
7. The method recited in claim 1, wherein the objects are of a single object type.
8. The method recited in claim 7, wherein the objects are of multiple object types.