1. A nonvolatile semiconductor memory system, comprising:
a memory array comprising a plurality of multi-bit memory cells; and,
a memory controller comprising:
a buffer memory adapted to store j-bit data programmed in selected memory cells among the plurality of memory cells;
a repair memory adapted to store i-bit data read from the selected memory cells;
a fail position detector adapted to determine the location of a bit error in the i-bit data based on a comparison between j-bit data read from the selected memory cells and the j-bit data stored in the buffer memory; and
a repair unit adapted to repair bit errors in the i-bit data stored in the repair memory.
2. The system of claim 1, wherein the buffer memory has a greater capacity than the repair memory.
3. The system of claim 1, wherein the memory controller further comprises a comparator adapted to perform the comparison.
4. The system of claim 1, wherein the memory controller further comprises an error correction unit adapted to correct errors in the i-bit data.
5. The system of claim 1, wherein the memory controller further comprises an error correction circuit adapted to correct errors in the i-bit data.
6. The system of claim 1, wherein the fail position detector determines the location of the bit error in relation to a cell scramble of the multi-bit memory cells.
7. The system of claim 1, wherein the i-bit data and the j-bit data each comprise a page or a block of data.
8. The system of claim 1, wherein the memory array comprises a NAND flash memory array.
9. A nonvolatile semiconductor memory system, comprising:
first through n-th memory chips, each comprising a plurality of multi-bit nonvolatile memory cells; and
a memory controller comprising:
first through m-th buffer memories each adapted to store j-bit data programmed in selected memory cells among the plurality of multi-bit nonvolatile memory cells in the first through n-th memory chips;
and first through p-th repair memories adapted to store i-bit data stored in the selected memory cells;
a fail position detector adapted to determine the location of a bit error in the i-bit data based on a comparison between j-bit data read from the selected memory cells and the j-bit data stored in the buffer memory; and
a repair unit adapted to repair bit errors in the i-bit data stored in the repair memory.
10. The system of claim 9, wherein n and m are both greater than one and the first through p-th repair memories comprises a single repair memory.
11. The system of claim 9, wherein the first through m-th buffer memories and the first through p-th repair memories comprise different regions of a single memory chip.
12. The system of claim 9, wherein n is equal to m.
13. The system of claim 9, wherein the memory controller further comprises a comparator adapted to perform the comparison.
14. The system of claim 9, wherein the memory controller further comprises an error correction unit adapted to correct errors in the i-bit data.
15. The system of claim 9, wherein the memory controller further comprises an error correction circuit adapted to correct errors in the i-bit data.
16. The system of claim 9, wherein the fail position detector determines the location of the bit error in relation to a cell scramble of the multi-bit memory cells.
17. The system of claim 9, wherein the i-bit data and the j-bit data each comprise a page or a block of data.
18. The system of claim 9, wherein one or more of the first through n-th memory chips comprises a NAND flash memory chip.
19. A method of performing a program operation in a multi-bit nonvolatile semiconductor memory system comprising a memory array including a plurality of multi-bit memory cells, and a memory controller, the method comprising:
programming i-bit data in selected memory cells of the memory array;
storing j-bit data in the memory controller;
programming the j-bit data in the selected memory cells;
determining whether the j-bit data was successfully programmed in the selected memory cells;
upon determining that the j-bit data was not successfully programmed in the selected memory cells, comparing the j-bit data stored in the selected memory cells with the j-bit data stored in the memory controller;
based on the comparison, determining the position of at least one bit error in the i-bit data stored in the selected memory cells; and
repairing the at least one bit error in the i-bit data.
20. The method of claim 19, further comprising:
upon determining that the j-bit data was successfully programmed in the selected memory cells, terminating the program operation.
21. The method of claim 19, further comprising:
upon determining that the j-bit data was not successfully programmed in the selected memory cells and before comparing the j-bit data stored in the selected memory cells with the j-bit data stored in the memory controller, reading the i-bit data from the selected memory cells into the memory controller and determining whether any bit errors in the i-bit data can be corrected by an error correction unit; and
upon determining that any errors in the i-bit data can be corrected by the error correction unit, terminating the program operation.
22. The method of claim 19, further comprising:
after repairing the at least one bit error in the i-bit data, correcting any remaining bit errors in the i-bit data using an error correction unit.
23. The method of claim 19, wherein the position of the at least one bit error in the i-bit data is determined in relation to a cell scramble of the multi-bit memory cells.
24. The system of claim 19, wherein one or more of the first through n-th memory chips comprises a NAND flash memory chip.
25. The method of claim 19, wherein the j-bit data and the i-bit data each comprise a page or a block of data.
26. A method of programming a nonvolatile memory comprising multi-bit nonvolatile memory cells, the method comprising:
defining a cell scramble for the memory cells; and
upon detecting a programming failure for j-bit data in a selected one of the memory cells, repairing previously programmed i-bit data in the selected memory cell in relation to the cell scramble.
27. The method of claim 26, further comprising:
correcting errors in the i-bit data using an error correction unit.
28. The method of claim 26, wherein the memory cells are two-bit nonvolatile memory cells; and
wherein the i-bit data is most significant bit (MSB) data and the j-bit data is least significant bit (LSB) data.
29. The system of claim 26, wherein the memory cells are two-bit nonvolatile memory cells; and
wherein the i-bit data is least significant bit (LSB) data and the j-bit data is most significant bit (MSB) data.
30. The method of claim 26, wherein the j-bit data and the i-bit data each comprise a page or a block of data.
31. The method of claim 26, wherein the nonvolatile memory comprises a NAND flash memory.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cleaning device comprising:
a cleaning portion that comes into contact with an image carrier that is adapted to carry a toner image; and
a pressing portion that presses the cleaning portion against the image carrier, the pressing portion including a clamping surface that clamps the cleaning portion from both sides in cooperation with the image carrier, and a protruding portion that protrudes from the clamping surface toward the image carrier.
2. The cleaning device according to claim 1, further comprising:
a rubbing roller that rubs the image carrier,
wherein the pressing portion includes a support bracket that supports the rubbing roller, and
the cleaning portion is a seal member that is pressed against an adjacent region by the support bracket, the adjacent region being adjacent to a rubbed region that is rubbed by the rubbing roller.
3. The cleaning device according to claim 2, further comprising:
a cleaning blade including an abutment edge that abuts against the rubbed region after the rubbing roller,
wherein the protruding portion includes a first end portion and a second end portion that is further away from the rubbing roller than the first end portion, and
the first end portion is located downstream of the second end portion with respect to a direction in which the adjacent region moves.
4. The cleaning device according to claim 3, wherein the abutment edge is located above a position at which the rubbing roller rubs the image carrier.
5. The cleaning device according to claim 4, further comprising a housing that accommodates the rubbing roller,
wherein the rubbing roller that comes into contact with the rubbed region via an opening portion formed in the housing conveys toner removed from the rubbed region and adhering to the rubbing roller to the interior of the housing.
6. The cleaning device according to claim 5, further comprising:
a separating plate that separates the toner from the rubbing roller, and
a discharge portion that discharges the toner separated by the separating plate out of the housing.
7. The cleaning device according to claim 1, wherein the protruding portion is a ridge.
8. The cleaning device according to claim 1, wherein the protruding portion is a protruding surface that is closer to the image carrier than the clamping surface.
9. An image forming apparatus comprising:
an image carrier that is adapted to carry a toner image;
a cleaning portion that comes into contact with the image carrier; and
a pressing portion that presses the cleaning portion against the image carrier, the pressing portion including a clamping surface that clamps the cleaning portion from both sides in cooperation with the image carrier, and a protruding portion that protrudes from the clamping surface toward the image carrier.
10. The image forming apparatus according to claim 9, further comprising:
a rubbing roller that rubs the image carrier,
wherein the pressing portion includes a support bracket that supports the rubbing roller, and
the cleaning portion is a seal member that is pressed against an adjacent region by the support bracket, the adjacent region being adjacent to a rubbed region that is rubbed by the rubbing roller.
11. The image forming apparatus according to claim 10, further comprising:
a cleaning blade including an abutment edge that abuts against the rubbed region after the rubbing roller,
wherein the protruding portion includes a first end portion and a second end portion that is further away from the rubbing roller than the first end portion, and
the first end portion is located downstream of the second end portion with respect to a direction in which the adjacent region moves.
12. The image forming apparatus according to claim 11, wherein the abutment edge is located above a position at which the rubbing roller rubs the image carrier.
13. The image forming apparatus according to claim 12, further comprising a housing that accommodates the rubbing roller,
wherein the rubbing roller that comes into contact with the rubbed region via an opening portion formed in the housing conveys toner removed from the rubbed region and adhering to the rubbing roller to the interior of the housing.
14. The image forming apparatus according to claim 13, further comprising:
a separating plate that separates the toner from the rubbing roller, and
a discharge portion that discharges the toner separated by the separating plate out of the housing.
15. The image forming apparatus according to claim 9, wherein the protruding portion is a ridge.
16. The image forming apparatus according to claim 9, wherein the protruding portion is a protruding surface that is closer to the image carrier than the clamping surface.