1. An array of polymers on a surface of a substrate, comprising a first layer on a solid support, said first layer including one or more dielectric coatings on said solid support and a second layer including a plurality of different and positionally distinct polymers disposed on said first layer in different features.
2. The array according to claim 1, wherein said one or more dielectric coatings is a dichroic antireflective coating.
3. The array according to claim 1, wherein said plurality of polymers comprises a plurality of oligonucleotides.
4. The array according to claim 1, wherein the one or more dielectric coatings is SiO2.
5. The array according to claim 1, wherein the one or more dielectric coatings comprises hydroxyl, carboxyl, amino, thiol, haloalkyl, 1,2-diol, aldehyde, acryloyl, maleimidyl or N-succinimidylcarboxylate groups used to connect the polymers to the first layer.
6. The array according to claim 1, wherein the size of a feature on said first layer of said substrate is smaller than about 20 \u03bcm.
7. The array according to claim 1, wherein the size of a feature on said first layer of said substrate is smaller than about 10 \u03bcm.
8. The array according to claim 1, wherein said first layer is derivatized by contacting said first layer with a silanation reagent.
9. The array according to claim 8, wherein said silanation reagent is selected from the group consisting on Bis-hydroxyethyl-3-aminopropyltriethoxysilane, N(2-hydroxyethyl)-N, N-bis(trimethoxysilylpropyl)amine and Bis(trimethoxysilyl)-ethane.
10. The array according to claim 1, wherein said first layer is derivatized and coated with functional groups protected with a photolabile protecting group.
11. The array according to claim 10, wherein said photolabile protecting group is MeNPOC.
12. The array according to claim 1, wherein said plurality of polymers comprises a plurality of polypeptides.
13. An array of polymers on a surface of a substrate, comprising a first layer on a solid support, said first layer including one or more dichroic antireflective coatings on said solid support and a second layer including a plurality of different and positionally distinct oligonucleotides disposed on said first layer in different features.
14. The array according to claim 13, wherein the one or more dichroic antireflective coatings is SiO2.
15. The array according to claim 13, wherein the one or more dielectric coatings comprises hydroxyl, carboxyl, amino, thiol, haloalkyl, 1,2-diol, aldehyde, acryloyl, maleimidyl or N-succinimidylcarboxylate groups used to connect the polymers to the first layer.
16. The array according to claim 13, wherein the size of a feature on said first layer of said substrate is smaller than about 20 \u03bcm.
17. The array according to claim 13, wherein the size of a feature on said first layer of said substrate is smaller than about 10 \u03bcm.
18. The array according to claim 13, wherein said first layer is derivatized by contacting said first layer with a silanation reagent.
19. The array according to claim 18, wherein said silanation reagent is selected from the group consisting on Bis-hydroxyethyl-3-aminopropyltriethoxysilane, N(2-hydroxyethyl)-N, N-bis(trimethoxysilylpropyl)amine and Bis(trimethoxysilyl)-ethane.
20. An array of polymers on a surface of a substrate, comprising a first layer on a solid support, said first layer including one or more dichroic antireflective coatings on said solid support and a second layer including a plurality of different and positionally distinct oligonucleotides disposed on said first layer in different features, wherein the size of a feature on said first layer of said substrate is smaller than about 10 \u03bcm, and wherein the one or more dichroic antireflective coatings absorbs greater than about 75% of photolytic light.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pulse width modulation regulator, comprising:
a first controller, wherein the first controller receives as input a clock signal and a first control signal and outputs a first pulse width modulator signal and a first enable signal;
a second controller, wherein the second controller receives as input an inverse of the clock signal and a second control signal and outputs a second pulse width modulated signal and a second enable signal;
wherein the first enable signal maintains the second pulse width modulated signal at first state when the first pulse width modulated signal has not increased to a desired pulse width,
wherein the second enable signal maintains the first pulse width modulated signal at a second state when the second pulse width modulated signal has not decreased to the desired pulse width; and
an OR gate for receiving as input the first and second pulse width modulated signals and for providing an output signal.
2. The regulator of claim 1, wherein at least the first or the second controller comprises:
a charge pump;
a comparator circuit coupled to the charge pump, the comparator circuit for providing a pulse width modulated signal; and
a latch circuit coupled to the charge pump for ensuring that the charge pump is adjusted such that an undershoot condition and an overshoot condition of the pulse width modulated signal is minimized.
3. The regulator of claim 2, wherein an input of the comparator circuit comprises an output of the charge pump.
4. The regulator of claim 2, wherein an input of the latch circuit comprises the pulse width modulated signal.
5. The regulator of claim 4, wherein the latch circuit transmits a first latch signal to the charge pump when the pulse width modulated signal is in a high state, wherein the first latch signal prevents the overshoot condition.
6. The regulator of claim 5, wherein the first latch signal prevents the output of the charge pump from increasing further.
7. The regulator of claim 4, wherein the latch circuit transmits a second latch signal to the charge pump when the pulse width modulated voltage is in a low state, wherein the second latch signal prevents the undershoot condition.
8. The regulator of claim 7, wherein the second latch signal prevents the output of the charge pump from decreasing further.
9. The regulator of claim 2, wherein the latch circuit comprises:
a first SR latch;
a second SR latch, wherein an input of the second SR latch comprises the pulse width modulated signal;
a first gate, wherein an input of the first gate comprises an output from the second SR latch and an input signal, wherein an output of the first gate comprises a first latch signal to the charge pump, wherein the first latch signal prevents the overshoot condition; and
a second gate, wherein an input of the second gate comprises an output from the first SR latch and the input signal, wherein an output of the second gate comprise a second latch signal to the charge pump, wherein the second latch signal prevents the undershoot condition.
10. The regulator of claim 9, wherein the latch circuit further comprises:
a first D flip-flop coupled between the first SR latch and the second gate; and
a second D flip-flop coupled between the second SR latch and the first gate.
11. The regulator of claim 2, wherein the comparator circuit comprises:
a clock circuit; and
an inverter coupled to an output of the clock circuit.
12. The regulator of claim 2, wherein the comparator circuit comprises:
a clock circuit; and
a pulse generator coupled to an input of the clock circuit.
13. A pulse width modulation regulator, comprising:
a first controller, wherein the first controller receives as input a clock signal and a first control signal and outputs a first pulse width modulator signal and a first enable signal;
a second controller, wherein the second controller receives as input an inverse of the clock signal and a second control signal and outputs a second pulse width modulated signal and a second enable signal;
wherein the first enable signal maintains the second pulse width modulated signal at first state when the first pulse width modulated signal has not increased to a desired pulse width,
wherein the second enable signal maintains the first pulse width modulated signal at a second state when the second pulse width modulated signal has not decreased to the desired pulse width; and
an OR gate for receiving as input the first and second pulse width modulated signals and for providing an output signal,
wherein at least the first or the second controller comprises:
a charge pump;
a comparator circuit coupled to the charge pump, the comparator circuit for providing a pulse width modulated signal; and
a latch circuit coupled to the charge pump for ensuring that the charge pump is adjusted such that an undershoot condition and an overshoot condition of the pulse width modulated signal is minimized.