1. An apparatus comprising:
a first side member and a second side member opposite to the first side member;
a foot bar coupling first ends of the first and second side members together;
a middle member coupling second ends of the first and second side members together, wherein the middle member is opposite to the foot bar, and the middle member is aligned along its entire length with a plane formed by the first and second side members; and
a top member coupling opposite ends of the middle member and the second ends of the first and second side members, wherein the middle member is opposite to the foot bar and the middle member is between the top member and the foot bar,
the first and second side members, the foot bar, and the middle member define a first opening sufficiently sized to accept a foot,
the middle member and the top member define a second opening, smaller than the first opening, sufficiently sized to accept a stirrup leather, and
wherein the top member comprises a first bend in a first direction, a second bend in a second direction, opposite to the first direction, a third bend in the first direction, and a fourth bend in the second direction.
2. The apparatus of claim 1 wherein the first bend in the first direction comprises a first angle away from the plane formed by the first and second side members.
3. The apparatus of claim 2 wherein the second bend in the second direction comprises a second angle toward the plane formed by the first and second side members.
4. The apparatus of claim 3 wherein the third bend in the first direction comprises a third angle toward the plane formed by the first and second side members, and the first angle is equal to the third angle, but in opposite directions.
5. The apparatus of claim 4 wherein the fourth bend in the second direction comprises a fourth angle into the plane formed by the first and second side members, and the fourth angle is equal to the first angle, but in opposite directions.
6. The apparatus of claim 5 wherein a segment of the top member, between the second and third bends, passes through the plane formed by the first and second side members.
7. The apparatus of claim 1 wherein the top member comprises a first segment from the first bend to the second bend, a second segment from the second bend to the third bend, and a third segment from the third bend to the fourth bend,
a first distance is from the first bend to the fourth bend,
a second distance comprises a sum of lengths of the first segment, second segment, and third segment, and
the second distance is greater than the first distance.
8. The apparatus of claim 1 wherein an area of the first opening is greater than an area of the second opening.
9. The apparatus of claim 1 comprising:
a foot pad, coupled to the foot bar, wherein a top surface of the foot pad is textured and faces the middle member.
10. The apparatus of claim 1 comprising:
a foot pad, coupled to the foot bar, wherein first and second portions of a top surface of the foot pad are textured, the first portion faces the middle member, and the second portion is angled relative to the first portion.
11. The apparatus of claim 1 wherein a section of the top member, between the second and third bends, is angled relative to the foot bar at about 45 degrees.
12. The apparatus of claim 1 wherein a section of the top member, between the second and third bends, is angled relative to the foot bar at an angle in a range between about 40 degrees to about 50 degrees.
13. The apparatus of claim 1 wherein the middle member extends from the first side member to the second side member without any bends.
14. The apparatus of claim 1 comprising:
a foot pad, coupled to the foot bar, wherein a top surface of the foot pad faces the middle member.
15. The apparatus of claim 1 comprising:
a foot pad, coupled to the foot bar, wherein the foot pad comprises an upper surface comprising first and second portions, the first portion faces the middle member, and the second portion is angled relative to the first portion.
16. The apparatus of claim 1 wherein the first side member comprises:
a first thickness near to the top member,
a second thickness near to the foot bar, and
the first thickness is less than the second thickness.
17. The apparatus of claim 1 wherein a section of the top member, between the second and third bends is angled relative to the foot bar at about 25 degrees.
18. The apparatus of claim 1 wherein a section of the top member, between the second and third bends is angled relative to the foot bar at an angle in a range between about 15 degrees to about 40 degrees.
19. An apparatus comprising:
a first side member and a second side member, opposite to the first side member;
a foot bar coupling first ends of the first and second side members together;
a middle member, coupling second ends of the first and second side members together, wherein the middle member is opposite to the foot bar, and the middle member is aligned along its entire length with a plane formed by the first and second side members; and
a top member, coupling opposite ends of the middle member and the second ends of the first and second side members, wherein the middle member is opposite to the foot bar and the middle member is between the top member and the foot bar,
the first and second side members, the foot bar, and the middle member define a first opening,
the middle member and the top member define a second opening, smaller than the first opening, and
the top member comprises a first bend in a first turn direction, a second bend in a second turn direction, different from the first direction, a third bend in the first direction, and a fourth bend in the second direction.
20. An apparatus comprising:
a first side member and a second side member, opposite to the first side member;
a foot bar coupling first ends of the first and second side members together;
a middle member, coupling second ends of the first and second side members together, wherein the middle member is opposite to the foot bar, and the middle member is aligned along its entire length with a plane formed by the first and second side members; and
a top member, coupling opposite ends of the middle member and the second ends of the first and second side members, wherein the middle member is opposite to the foot bar and the middle member is between the top member and the foot bar,
the first and second side members, the foot bar, and the middle member define a first opening,
the middle member and the top member define a second opening, smaller than the first opening, and
the top member comprises a first bend in a first direction, a second bend in a second direction, different from the first direction, a third bend in the first direction, and a fourth bend in the second direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of offset compensation in a digital to radio frequency (RF) amplitude converter (DRAC), said method comprising the steps of:
coupling a plurality of transistors to positive outputs and negative outputs generated by a sigma-delta modulator;
using a clock signal to enable a group of said transistors coupled to said positive outputs;
using an inverted clock signal to enable a group of said transistors coupled to said negative outputs; and
summing outputs of said transistors coupled to said positive outputs and said transistors coupled to said negative outputs to yield an offset compensated output signal.
2. The method according to claim 1, wherein said sigma-delta modulator comprises a 3rd order sigma-delta modulator.
3. The method according to claim 1, wherein each said transistor comprises a metal oxide semiconductor (MOS) device having a gate, drain and source.
4. The method according to claim 1, wherein said clock signal is generated by a digitally controlled oscillator (DCO).
5. The method according to claim 1, further comprising the step of coupling said offset compensated output signal to a matching network.
6. The method according to claim 5, wherein said output of said matching network is coupled to an external power amplifier and antenna.
7. The method according to claim 1, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).
8. The method according to claim 1, adapted to be implemented in a Field Programmable Gate Array (FPGA).
9. The method according to claim 1, wherein said inverted clock signal is an inversion of said clock signal.
10. The method according to claim 1, wherein said transistors are driving transistors.
11. A digital to radio frequency (RF) amplitude converter apparatus, comprising:
a plurality of transistors coupled to positive outputs and negative outputs generated by a sigma-delta modulator;
first means for driving transistors coupled to said positive outputs using a clock signal;
second means for driving transistors coupled to said negative outputs using an inverted version of said clock signal; and
third means for summing the output of each transistor to yield an offset compensated output signal.
12. The apparatus according to claim 11, wherein said sigma-delta modulator comprises a 3rd order sigma-delta modulator.
13. The apparatus according to claim 11, wherein each said transistor comprises a metal oxide semiconductor (MOS) device having a gate, drain and source.
14. The apparatus according to claim 11, wherein said clock signal is generated by a digitally controlled oscillator (DCO).
15. The apparatus according to claim 11, further comprising a matching network adapted to receive said offset compensated output signal.
16. The apparatus according to claim 15, further comprising an external power amplifier and antenna coupled to the output of said matching network.
17. The apparatus according to claim 11, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).
18. The apparatus according to claim 11, adapted to be implemented in a Field Programmable Gate Array (FPGA).
19. A transmit buffer, comprising:
a plurality of gates arranged in a parallel array, wherein a first portion of said gates are coupled to one or more positive outputs generated by a sigma-delta modulator, a second portion of said gates are coupled to one or more negative outputs generated by said sigma-delta modulator;
first means for driving the gates coupled to said positive outputs with a clock signal;
second means for driving the gates coupled to said negative outputs with an inverted version of said clock signal;
a plurality of transistors, the output of each gate coupled to one of said transistors; and
a matching network coupled to the output of each transistor and operative to generate an offset compensated radio frequency (RF) output signal.
20. The apparatus according to claim 19, wherein said plurality of gates comprises a plurality of AND gates.
21. The apparatus according to claim 19, wherein said plurality of gates comprises a plurality of pass-gate type AND gates.
22. The apparatus according to claim 19, wherein said sigma-delta modulator comprises a 3rd order sigma-delta modulator.
23. The apparatus according to claim 19, wherein each transistor comprises a metal oxide semiconductor (MOS) device having a gate, drain and source.
24. The apparatus according to claim 19, wherein said clock signal is generated by a digitally controlled oscillator (DCO).
25. The apparatus according to claim 19, further comprising an external power amplifier and antenna coupled to the output of said matching network.
26. The apparatus according to claim 19, adapted to be implemented in an Application Specific Integrated Circuit (ASIC).
27. The apparatus according to claim 19, adapted to be implemented in a Field Programmable Gate Array (FPGA).
28. A digital to radio frequency (RF) amplitude converter apparatus, comprising:
a plurality of switches coupled to positive outputs and negative outputs generated by a digital modulator;
first means for driving a portion of said switches coupled to said positive outputs with a clock signal;
second means for driving a second portion of said switches coupled to said negative outputs with an inverted version of said clock signal; and
third means for summing the output of each switch to yield an output signal.
29. A digital to radio frequency (RF) amplitude converter apparatus, comprising:
a plurality of switches coupled to positive outputs and negative outputs generated by a digital modulator;
first means for driving a first portion of said switches coupled to said positive outputs with a clock signal;
second means for driving a second portion of said switches coupled to said negative outputs with a different phase of said clock signal; and
third means for summing the output of each switch to yield an output signal.
30. A method of offset compensation in a digital to radio frequency (RF) amplitude converter (DRAC), said method comprising the steps of:
coupling a plurality of transistors to positive outputs and negative outputs generated by a sigma-delta modulator;
coupling first driving transistors to said positive outputs using a clock signal;
coupling second driving transistors to said negative outputs using a different phase of said clock signal; and
summing outputs of said plurality of transistors to yield an offset compensated output signal.
31. A method of offset compensation in a digital to radio frequency (RF) amplitude converter (DRAC), said method comprising the steps of:
coupling respective ones of a first plurality of transistors to respective positive outputs of a modulator;
coupling respective ones of a second plurality of transistors to respective negative outputs of said modulator;
a first clock signal enabling said first plurality of transistors;
a second clock signal enabling said second plurality of transistors; and
summing outputs of said first plurality of transistors and second plurality of transistors to yield an offset compensated output signal.
32. A transmit buffer, comprising:
a plurality of gates arranged in a parallel array, wherein a first portion of said gates are coupled to one or more positive outputs generated by a sigma-delta modulator, a second portion of said gates are coupled to one or more negative outputs generated by said sigma-delta modulator;
circuitry for driving the gates coupled to said positive outputs with a first clock signal;
circuitry for driving the gates coupled to said negative outputs with a second clock signal;
a plurality of transistors, an output of each gate coupled to one of said transistors; and
a matching network coupled to the output of each transistor and operative to generate an offset compensated radio frequency (RF) output signal.
33. The transmit buffer of claim 32, wherein said second clock signal is an inversion of said first clock signal.
34. A digital to radio frequency (RF) amplitude converter apparatus, comprising:
a plurality of switches coupled to positive and negative outputs generated by a digital modulator;
circuitry for driving a first portion of said switches coupled to said positive outputs with a first clock signal;
circuitry for driving a second portion of said switches coupled to said positive outputs with a first clock signal;
a plurality of transistors, an output of each gate coupled to one said transistors; and
circuitry for summing the output of each switch to yield an output signal.
35. The digital to radio frequency (RF) amplitude converter apparatus of claim 34, wherein said second clock signal is an inversion of said first clock signal.