1-20. (canceled)
21. A method, comprising:
forming a detach layer below a surface of a first substrate; and
forming at least one pn junction between the detach layer and surface of the first substrate.
22. The method of claim 21, wherein the pn junction includes single crystal semiconductor material.
23. The method of claim 21, further including forming a conductive layer on the surface of the first substrate.
24. The method of claim 23, further including providing an inter-layer dielectric layer with a second conductive layer on its surface.
25. The method of claim 24, further including bonding the first and second conductive layers together.
26. The method of claim 25, further including removing a portion of the first substrate between the detach layer and an opposed surface of the first substrate.
27. The method of claim 21, wherein the detach layer includes an oxide or porous semiconductor region.
28. The method of claim 21, wherein the pn junction is formed between blanket layers of oppositely doped semiconductors.
29. A method, comprising:
providing a first substrate having a detach layer below its surface and a first plurality of differently doped semiconductor layers between the detach layer and surface of the first substrate;
providing a second substrate which carries an inter-layer dielectric layer having a via and interconnection line; and
bonding the inter-layer dielectric layer to the first substrate.
30. The method of claim 29, further including providing a first conductive layer on the substrate so that the inter-layer dielectric layer and first substrate are bonded through the first conductive line.
31. The method of claim 29, further including removing a portion of the first substrate so that the first plurality of differently doped semiconductor layers are carried by the second substrate.
32. The method of claim 31, further including providing a second conductive layer on an exposed surface of the first plurality of differently doped semiconductor layers.
33. The method of claim 32, further including providing a third substrate having a detach layer below its surface and a second plurality of differently doped semiconductor layers between the detach layer and surface of the third substrate.
34. The method of claim 33, wherein the first and second plurality of differently doped semiconductor layers are blanket layers.
35. The method of claim 33, further including providing a third conductive layer on the surface of the third substrate.
36. The method of claim 35, further including bonding the third substrate to the first plurality of differently doped semiconductor layers through the second and third conductive layers.
37. The method of claim 36, further including removing a portion of the third substrate so that the second plurality of differently doped semiconductor layers is carried by the second substrate.
38. The method of claim 37, wherein the first and second plurality of differently doped semiconductor layers include single crystal semiconductor material.
39. The method of claim 29, wherein the detach layer is formed by implanting hydrogen.
40. A method, comprising:
providing a substrate which carries a first inter-layer dielectric layer;
providing a first stackable add-on layer;
bonding the first stackable add-on layer to the first inter-layer dielectric layer; and
processing the first stackable add-on layer to form a first vertically oriented semiconductor device.
41. The method of claim 40, wherein the first stackable add-on layer includes single crystalline semiconductor material.
42. The method of claim 40, wherein the first vertically oriented semiconductor device includes a stack of differently doped semiconductor layers.
43. The method of claim 42, further including forming a gate dielectric around the stack of differently doped semiconductor layers, and forming a gate electrode around the gate dielectric.
44. The method of claim 43, wherein the gate dielectric is formed at a temperature below about 650\xb0 C.
45. The method of claim 43, wherein the gate electrode includes a metal.
46. The method of claim 43, wherein the stack of differently doped semiconductor layers, gate dielectric, and gate electrode operate as a memory device.
47. The method of claim 43, wherein the gate dielectric includes an oxide-nitride-oxide layer stack of materials.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of correcting ROM bit errors in a ROM embedded DRAM, comprising:
programming a ROM section of a ROM embedded DRAM;
encoding on the ROM embedded DRAM in error correcting code (ECC) circuitry the ROM data;
decoding read ROM data before presenting the data to a user; and
correcting the ROM data if the ROM bit data if the ROM bit data is in error.
2. The method of claim 1, wherein the error correcting code circuitry is chosen from a group consisting of:
parity, Hamming code, modified Hamming code, Gray code, polynomial checking, and cyclical redundancy checking.
3. The method of claim 1, wherein decoding comprises:
error correcting with parity checking.
4. The method of claim 3, wherein error correcting with parity checking comprises:
comparing the parity check bit with the read ROM bit; and
inverting the read ROM bit if the parity bit indicates an error.
5. The method of claim 1, wherein decoding and correcting further comprise:
receiving a row and column address to read data from a ROM section;
reading an encoded ROM bit;
correcting the read ROM bit if necessary; and
presenting the corrected ROM bit as output data.
6. The method of claim 5, wherein correcting comprises:
decoding the read ROM bit with error correcting circuitry;
comparing the decoded ROM bit with the actual ROM bit; and
correcting if the decoded ROM bit differs from the read ROM bit.
7. The method of claim 1, wherein decoding comprises:
error correcting with ECC circuitry.
8. The method of claim 7, wherein error correcting with ECC circuitry comprises:
generating an ECC corrected ROM bit from a read ROM bit;
comparing the ECC corrected bit with the read ROM bit; and
correcting the read ROM bit if the ECC corrected ROM bit and the read ROM bit do not match.
9. The method of claim 1, wherein encoding ROM data in error correction circuitry is performed during fabrication of the ROM embedded DRAM.
10. The method of claim 1, wherein correcting further comprises:
receiving a row and column address to read data from the ROM section;
reading an encoded ROM bit;
correcting the read ROM bit if necessary; and
presenting the corrected ROM bit as output data.
11. The method of claim 10, wherein correcting comprises:
decoding the read ROM bit with the error correcting circuitry;
comparing the decoded ROM bit with the actual ROM bit; and
correcting if the decoded ROM bit differs from the read ROM bit.
12. The method of claim 10, wherein decoding comprises:
error correcting with the ECC circuitry.
13. The method of claim 12, wherein error correcting with the ECC circuitry comprises:
generating an ECC corrected ROM bit from a read ROM bit;
comparing the ECC corrected bit with the read ROM bit; and
correcting the read ROM bit if the ECC corrected ROM bit and the read ROM bit do not match.
14. The method of claim 10, wherein decoding comprises:
error correcting with parity checking.
15. The method of claim 14, wherein error correcting with parity checking comprises:
comparing the parity check bit with the read ROM bit; and
inverting the read ROM bit if the parity bit indicates an error.
15. The method of claim 1, wherein programming a ROM section of a ROM embedded DRAM comprises:
hard programming an error correction portion of the ROM bits of the ROM embedded DRAM.
16. The method of claim 15, wherein hard programming comprises:
eliminating a cell dielectric to short cell plates to a program voltage.
17. The method of claim 15, wherein hard programming comprises:
fabricating an electrical plug between cell plates and shorted to a program voltage.
18. The method of claim 15, wherein hard programming comprises:
programming using an anti-fuse programming technique,
19. The method of claim 15, wherein hard programming comprises:
providing a high leakage path through an active area to a substrate.
20. A method of correcting ROM bit errors in a ROM embedded DRAM, comprising:
programming a ROM section of a ROM embedded DRAM with a first portion of ROM cells dedicated to memory operations and a second portion of the ROM cells dedicated to error correction;
encoding error correction on the ROM embedded DRAM second section;
decoding read ROM data before presenting the data to a user; and
correcting the ROM data if the ROM bit data if the ROM bit data is in error.
21. The method of claim 20, wherein the error correcting code circuitry is chosen from a group consisting of:
parity, Hamming code, modified Hamming code, Gray code, polynomial checking, and cyclical redundancy checking.
22. The method of claim 20, wherein decoding comprises:
error correcting with parity checking.
23. The method of claim 22, wherein error correcting with parity checking comprises:
comparing the parity check bit with the read ROM bit; and
inverting the read ROM bit if the parity bit indicates an error.
24. The method of claim 20, wherein decoding and correcting further comprise:
receiving a row and column address to read data from a ROM section;
reading an encoded ROM bit;
correcting the read ROM bit if necessary; and
presenting the corrected ROM bit as output data.
25. The method of claim 24, wherein correcting comprises:
decoding the read ROM bit with error correcting circuitry;
comparing the decoded ROM bit with the actual ROM bit; and
correcting if the decoded ROM bit differs from the read ROM bit.