1460911629-724014b6-daa8-4da1-90ad-f8cd8492d761

1. A display device comprising:
a first display panel;
a first protective layer included in the first display panel;
a second display panel;
a second protective layer included in the second display panel;
a connection part that connects the first display panel and the second display panel; and
a first flexible substrate included in the first display panel and the second display panel, a portion of the first flexible substrate being included in the connection part, and the first protective layer and the second protective layer being layered on the first flexible substrate; and
a second flexible substrate included in the first display panel and the second display panel, a portion of the second flexible substrate being included in the connection part,
wherein the first display panel includes:
a first portion of the first flexible substrate;
a first portion of the second flexible substrate opposed to the first portion of the first flexible substrate;
a first display part arranged between the first portion of the first flexible substrate and the first portion of the second flexible substrate; and
a first sealing member that surrounds the outer periphery of the first display part so as to seal the first display part between the first portion of the first flexible substrate and the first portion of the second flexible substrate,

wherein the second display panel includes:
a second portion of the first flexible substrate;
a second portion of the second flexible substrate opposed to the second portion of the first flexible substrate;
a second display part arranged between the second portion of the first flexible substrate and the second portion of the second flexible substrate; and
a second sealing member that surrounds the outer periphery of the second display part so as to seal the second display part between the second portion of the first flexible substrate and the second portion of the second flexible substrate,

wherein the first flexible substrate includes a third portion arranged between the first display part and the second display part,
wherein the second flexible substrate includes a third portion arranged between the first display part and the second display part,
wherein the connection part includes the third portion of the first flexible substrate and the third portion of the second flexible substrate,
wherein a strength of the first protective layer is higher than a strength of the first flexible substrate, and
wherein a strength of the second protective layer is higher than the strength of the first flexible substrate.
2. The display device according to claim 1, the connection part includes no electrical circuit.
3. The display device according to claim 1, wherein
the first protective layer is inflexible and the first protective layer keeps the first display part flat, and
the second protective layer is inflexible and the second protective layer keeps the second display part flat.
4. An electronic apparatus comprising:
a first display panel;
a first protective layer included in the first display panel;
a second display panel;
a second protective layer included in the second display panel;
a first flexible substrate included in the first display panel and the second display panel, a portion of the first flexible substrate being included in the connection part, and the first protective layer and the second protective layer being layered on the first flexible substrate; and
a second flexible substrate included in the first display panel and the second display panel, a portion of the second flexible substrate being included in the connection part,
wherein the first display panel includes:
a first portion of the first flexible substrate;
a first portion of the second flexible substrate opposed to the first portion of the first flexible substrate;
a first display part arranged between the first portion of the first flexible substrate and the first portion of the second flexible substrate; and
a first sealing member that surrounds the outer periphery of the first display part so as to seal the first display part between the first portion of the first flexible substrate and the first portion of the second flexible substrate,

wherein the first flexible substrate includes a third portion arranged between the first display part and the second display part,
wherein the second flexible substrate includes a third portion arranged between the first display part and the second display part,
wherein the connection part includes the third portion of the first flexible substrate and the third portion of the second flexible substrate,
wherein a strength of the first protective layer is higher than a strength of the first flexible substrate, and
wherein a strength of the second protective layer is higher than the strength of the first flexible substrate.
5. A method for manufacturing a display device including a first display panel, and a second display panel, and a connection part that connects the first display panel and the second display panel, the method comprising:
forming a first display part and a second display part protected by a protective layer, the protective layer being arranged on a first flexible substrate; and
forming a first protective layer in the first display panel and the second protective layer in the second display panel by removing a portion of the protective layer corresponding to the space having a predetermined width,
wherein the first display panel includes:
a first portion of the first flexible substrate;
a first portion of a second flexible substrate opposed to the first portion of the first flexible substrate;
the first display part arranged between the first portion of the first flexible substrate and the first portion of the second flexible substrate; and
a first sealing member that surrounds the outer periphery of the first display part so as to seal the first display part between the first portion of the first flexible substrate and the first portion of the second flexible substrate,

wherein the second display panel includes:
a second portion of the first flexible substrate;
a second portion of the second flexible substrate opposed to the second portion of the first flexible substrate;
the second display part arranged between the second portion of the first flexible substrate and the second portion of the second flexible substrate; and
a second sealing member that surrounds the outer periphery of the second display part so as to seal the second display part between the second portion of the first flexible substrate and the second portion of the second flexible substrate,

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An apparatus, comprising:
a first memory cell coupled to a first bit line;
a second memory cell coupled to a second bit line;
an address decoder coupled to the first and second memory cells to enable access to the first and second memory cells; and
a comparator circuit coupled to the first and second bit lines to compare the voltage level on the first bit line with the voltage level on the second bit at a time when data is output from the first memory cell on the first bit line and from the second memory cell on the second bit line.
2. The apparatus of claim 1, wherein the address decoder decodes part of a memory address.
3. The apparatus of claim 1, wherein the first and second memory cells are dynamic RAM memory cells.
4. The apparatus of claim 1, wherein the first and second memory cells are static RAM memory cells.
5. The apparatus of claim 1, wherein the comparator circuit is comprised of a single comparator with a first input coupled to the first bit line and a second input coupled to the second bit line.
6. The apparatus of claim 5, wherein the output of the comparator is coupled to a latch to store an indication that the voltage level on the first bit line differs substantially from the voltage level on the second bit line.
7. The apparatus of claim 6, wherein the time at which the latch is triggered is adjustable.
8. The apparatus of claim 6, wherein the latch is a sticky latch that is triggered to latch an indication that the voltage level on the first bit line differs substantially from the voltage level on the second bit line at any time that such an indication takes place.
9. The apparatus of claim 1, wherein the comparator circuit is comprised of:
a subtracting circuit with a first input coupled to the first bit line and a second input coupled to the second bit line;
a first comparator coupled to the output of the subtracting circuit; and
a second comparator coupled to the output of the subtracting circuit.
10. The apparatus of claim 9, wherein:
the output of the first comparator is coupled to a first latch to store an indication that difference in voltage levels between the first bit line and the second bit line has risen above a first reference voltage; and
the output of the second comparator is coupled to a second latch to store an indication that the difference in voltage levels between the first bit line and the second bit line has dropped below a second reference voltage.
11. The apparatus of claim 10, wherein the first and second reference voltages are adjustable.
12. The apparatus of claim 10, wherein the time at which the first and second latches are triggered is adjustable.
13. The apparatus of claim 10, wherein the first and second latches are sticky latches such that the first latch will latch any indication that the differences in voltage level between the first and second bit lines has risen above the first voltage reference and the second latch will latch any indication that the differences in voltage level between the first and second bit lines has dropped below the second reference voltage.
14. A method, comprising:
writing identical values to the first and second memory cells;
coupling a first memory cell to a first bit line;
coupling a second memory cell to a second bit line;
coupling the first and second bit lines to inputs of a comparator circuit;
reading the identical values from the first memory cell through the first bit line and from the second memory cell through the second bit line;
comparing the voltage levels on the first and second bit lines.
15. The method of claim 14, further comprising latching an indication from the comparator circuit that the voltage level of the first bit line differs substantially from the voltage level of the second bit line.
16. The method of claim 14, further comprising setting the degree to which the difference in voltage levels between the first bit line and the second bit line is substantial.
17. A comparator circuit in a memory array comprising:
a first input coupled to a first bit line that is coupled to a first memory cell in the memory array;
a second input coupled to a second bit line that is coupled to a second memory cell in the memory array; and
an output coupled to a sticky latch.
18. The comparator circuit of claim 17, wherein the comparator circuit is coupled to a multiplexer to disconnect the second bit line, and to connect a third bit line that is coupled the first memory cell in the memory array.