1. A voltage controlling circuit with power sharing components, the circuit comprising:
a voltage regulator for controlling an output voltage for a load;
a first transistor connected in series with the voltage regulator for sharing power dissipation with the voltage regulator, the first transistor being disposed between an input of the voltage regulator and an electrical reference voltage;
a shunt voltage regulator connected between the first transistor and the electrical reference voltage, the shunt voltage regulator having a feedback input that controls the first transistor;
a second transistor connected between the first transistor and the shunt voltage regulator, wherein a gate of the second transistor is connected to the shunt voltage regulator; and
a current regulating device directly connected between the source of the first transistor and the gate of the first transistor.
2. The circuit according to claim 1, wherein the source of the first transistor is connected to a circuit input voltage.
3. The circuit according to claim 2, wherein a drain of the first transistor is connected to an input voltage of a voltage regulator.
4. The circuit according to claim 3, wherein the gate of the first transistor is connected to the source of the first transistor through a resistor.
5. The circuit according to claim 4, wherein the second transistor is connected between the gate of the first transistor and an electrical reference voltage.
6. The circuit according to claim 5, wherein a source of the second transistor is connected to an electrical reference voltage through a resistor.
7. The circuit according to claim 6, wherein a drain of the second transistor is connected to the gate of the first transistor.
8. The circuit according to claim 7, wherein a gate of the second transistor is connected to the source of the first transistor through a resistor.
9. The circuit according to claim 5, wherein the second transistor controls the first transistor through the shunt voltage regulator.
10. The circuit according to claim 9, wherein the cathode of the second voltage regulator is connected to the gate of the second transistor and to a circuit power source reference.
11. The circuit according to claim 10, wherein the cathode of the second voltage regulator is connected to a resistor and the other end of the resistor is connected to the circuit power source reference.
12. The circuit according to claim 11, wherein a feedback input of the second voltage regulator is connected to a percentage of the input voltage of the first voltage regulator.
13. The circuit according to claim 12, wherein the feedback input of the second voltage regulator is connected to a first resistor and the other end of the resistor is connected to a circuit reference.
14. The circuit according to claim 13, wherein the feedback input of the second voltage regulator is connected to a second resistor and the other end of the resistor is connected to the input of the first voltage regulator.
15. The circuit according to claim 1, wherein shunt voltage regulator is a zener diode.
16. The circuit according to claim 1, wherein the current regulating device is a zener diode.
17. The circuit according to claim 1, wherein the zener diode has a cathode end directly connected to the source of the first transistor and an anode end direct connected to the gate of the first transistor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A transistor array formed in a semiconductor material of a first conductivity type, the transistor array comprising:
a plurality of spaced-apart source strips of a second conductivity type, the source strips contacting the semiconductor material;
a plurality of spaced-apart drain strips of the second conductivity type, the drain strips contacting the semiconductor material;
a plurality of channel strips of the semiconductor material, the channel strips lying between the source and drain strips so that each channel strip lies between and contacts a source strip and a drain strip;
a plurality of isolation strips, the plurality of isolation strips contacting the plurality of channel strips;
a plurality of gate strips, the gate strips contacting the plurality of isolation strips; and
a localized region that contacts a first channel strip and a second channel strip.
2. The transistor array of claim 1 wherein the localized region includes:
a first isolation region that contacts the semiconductor material and extends from the first channel strip to the second channel strip;
a second isolation region spaced apart from the first isolation region, the second isolation region contacting the semiconductor material and extending from the first channel strip to the second channel strip; and
an ESD region that contacts the semiconductor material, a portion of the first channel strip, and a portion of the second channel strip, the ESD region lying between and contacting the first and second isolation regions.
3. The transistor array of claim 2 wherein the ESD region includes a drain ballasting region of the second conductivity type, the drain ballasting region contacting the semiconductor material, the portion of the first channel strip, the portion of the second channel strip, the first isolation region, and the second isolation region.
4. The transistor array of claim 3 wherein at least one channel strip lies between the first and second channel strips.
5. The transistor array of claim 4 and further comprising a plurality of contacts that contact the drain ballasting region, each contact lying substantially midway between the first and second channel strips.
6. The transistor array of claim 2 wherein the ESD region includes:
a well of the second conductivity type that contacts the semiconductor material, the first isolation region, and the second isolation region;
a first doped region of the second conductivity type, the first doped region contacting the portion of the first channel region and the well, and having a dopant concentration that is greater than a dopant concentration of the well; and
a second doped region of the second conductivity type, the second doped region contacting the portion of the second channel region and the well, the first and second doped regions being spaced apart and having substantially equal dopant concentrations.
7. The transistor array of claim 6 wherein the ESD region further includes:
a third doped region of the first conductivity type, the third doped region contacting the first doped region and the well;
a fourth doped region of the second conductivity type, the fourth doped region contacting the third doped region and the well; and
a fifth doped region of the first conductivity type, the fifth doped region contacting the second doped region, the fourth doped region, and the well.
8. The transistor array of claim 7 and further comprising a conductive line electrically connected to the third, fourth, and fifth doped regions.
9. The transistor array of claim 6 wherein the ESD region further includes a third doped region of the first conductivity type, the third doped region contacting the first doped region, the second doped region, and the well.
10. The transistor array of claim 9 and further comprising a conductive line electrically connected to the first, second, and third doped regions.
11. The transistor array of claim 2 wherein the localized region can lie anywhere within the array.
12. The transistor array of claim 2 wherein when a gate voltage is applied to the plurality of gate strips, a current flows from the localized region to first and second source strips that lie adjacent to the first and second channel strips.
13. The transistor array of claim 12 wherein when an ESD pulse is applied to the drain strips, an ESD current flows from the localized region to the semiconductor material.
14. The transistor array of claim 13 wherein when the ESD pulse is applied, the localized region prevents the voltage on the drain strips from exceeding a predetermined value.
15. The transistor array of claim 2 wherein the channel strips have different lengths.
16. The transistor array of claim 2 wherein a plurality of channel strips lie between the first and second channel strips.