1. A method for manufacturing an electronic device including a package, comprising:
plating a lid of the package such that a plating film is formed on a surface of the lid;
removing burrs on the plating film on the lid surface by chemical polishing;
inserting the electronic component in a package body through an opening thereof located on one of sides thereof; and
attaching the lid to the package body.
2. The method according to claim 1, wherein the lid is plated with nickel.
3. The method according to claim 1, wherein the lid is attached to the package body by welding.
4. The method according to claim 1, wherein the step of removing burrs includes:
preparing a solution composed of chemical abrasive and water in proportions of 1:1; and
soaking the lid in the solution for one to ten minutes at a room temperature.
5. The method according to claim 4, wherein the chemical abrasive is a hydrogen peroxide base abrasive.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a partially depleted semiconductor-on-insulator structure having a three terminal JFET constructed thereon;
wherein the three terminal JFET comprises:
a source region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure; and
a gate region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure, wherein a gate-to-channel junction is formed deep enough in the semiconductor layer such that the channel region abuts an insulating layer of the semiconductor-on-insulator structure.
2. The semiconductor device of claim 1, wherein:
the semiconductor layer of the partially depleted semiconductor-on-insulator structure comprises a thickness ranging from 50-70 nm;
the gate region comprises a thickness ranging from 20-30 nm; and
the channel region comprises a thickness of 20-40 nm.
3. The semiconductor device of claim 1, wherein the location of the gate-to-channel junction within the semiconductor layer is based at least in part upon an implant dose and energy of dopants for the channel region.
4. The semiconductor device of claim 1, wherein the semiconductor layer comprises one of silicon or silicon-germanium.
5. A semiconductor device, comprising:
a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon;
wherein the four terminal JFET comprises a source region, a drain region, a channel region, a front gate region, and a back gate region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure; and
wherein the three terminal JFET comprises:
a source region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure; and
a gate region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure, wherein a gate-to-channel junction of the three terminal JFET is formed deep enough in the semiconductor layer such that the channel region of the three terminal JFET abuts an insulating layer of the semiconductor-on-insulator structure.
6. The semiconductor device of claim 5, wherein:
the semiconductor layer of the partially depleted semiconductor-on-insulator structure comprises a thickness ranging from 50-70 nm;
the gate region of the three terminal JFET comprises a thickness ranging from 20-30 nm; and
the channel region of the three terminal JFET comprises a thickness of 20-40 nm.
7. The semiconductor device of claim 5, wherein the location of the gate-to-channel junction within the semiconductor layer is based at least in part upon an implant dose and energy of dopants for the channel region of the three terminal JFET.
8. The semiconductor device of claim 5, wherein the three terminal JFET and the four terminal JFET are used in the same SRAM cell.
9. The semiconductor device of claim 5, wherein the three terminal JFET and the four terminal JFET are used in the same FPGA device.
10. The semiconductor device of claim 5, wherein the semiconductor layer comprises one of silicon or silicon-germanium.
11. The semiconductor device of claim 5, wherein the four terminal JFET comprises an n-channel transistor and the three terminal JFET comprises a p-channel transistor.
12. The semiconductor device of claim 5, wherein the four terminal JFET comprises a p-channel transistor and the three terminal JFET comprises an n-channel transistor.
13. The semiconductor device of claim 5, wherein the four terminal JFET comprises an n-channel transistor and the three terminal JFET comprises an n-channel transistor.
14. The semiconductor device of claim 5, wherein the four terminal JFET comprises a p-channel transistor and the three terminal JFET comprises a p-channel transistor.
15. A semiconductor device, comprising:
a partially depleted semiconductor-on-insulator structure having both a three terminal JFET and a four terminal JFET constructed thereon;
wherein the four terminal JFET comprises a source region, a drain region, a channel region, a front gate region, and a back gate region formed in a semiconductor layer of the partially depleted semiconductor-on-insulator structure; and
wherein the three terminal JFET comprises:
a source region formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a drain region spaced apart from the source region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a channel region between the source region and the drain region and formed in the semiconductor layer of the partially depleted semiconductor-on-insulator structure;
a front gate region formed at one surface of the semiconductor layer of the partially depleted semiconductor-on-insulator structure; and
a back gate region formed at another surface of the semiconductor layer of the partially depleted semiconductor-on-insulator structure such that it abuts an insulating layer of the semiconductor-on-insulator structure, wherein the back gate region comprises a thickness that is small enough such that it does not hold a charge.
16. The semiconductor device of claim 15, wherein:
the semiconductor layer of the partially depleted semiconductor-on-insulator structure comprises a thickness ranging from 50-70 nm;
the front gate region comprises a thickness ranging from 20-30 nm; and
the channel region comprises a thickness of 20-40 nm.
17. The semiconductor device of claim 15, wherein the thickness of the back gate region comprises 10 nm or less.
18. The semiconductor device of claim 15, wherein the location of the gate-to-channel junction within the semiconductor layer is based at least in part upon an implant dose and energy of dopants for the channel region.
19. The semiconductor device of claim 15, wherein the back gate region is not tied to an external terminal.
20. The semiconductor device of claim 15, wherein the three terminal JFET and the four terminal JFET are used in the same SRAM cell.
21. The semiconductor device of claim 15, wherein the three terminal JFET and the four terminal JFET are used in the same FPGA device.
22. The semiconductor device of claim 15, wherein the semiconductor layer comprises one of silicon or silicon-germanium.
23. The semiconductor device of claim 15, wherein the four terminal JFET comprises an n-channel transistor and the three terminal JFET comprises a p-channel transistor.
24. The semiconductor device of claim 15, wherein the four terminal JFET comprises a p-channel transistor and the three terminal JFET comprises an n-channel transistor.
25. The semiconductor device of claim 15, wherein the four terminal JFET comprises an n-channel transistor and the three terminal JFET comprises an n-channel transistor.
26. The semiconductor device of claim 15, wherein the four terminal JFET comprises a p-channel transistor and the three terminal JFET comprises a p-channel transistor.
27. The semiconductor device of claim 15, wherein the back gate region shields the channel region from charges that may accumulate at the interface between the semiconductor layer and the insulating layer.