1. A method comprising:
transmitting an outgoing RF signal to an antenna through a directional device having a first terminal receiving the outgoing RF signal and having a second terminal transmitting most of the outgoing RF signal to the antenna;
receiving a RF signal reflected by an RF tag from a third terminal of the directional device;
generating a demodulated vector signal from a spurious R signal and the RF signal received by the antenna;
generating a group of at least two control-parameters from an error vector related to the demodulated vector signal based on a look up table containing a frequency dependent relationship between the group of at least two control-parameters and the error vector;
setting the impedance of a controllable-variable-impedance element with the group of at least two control-parameters; and
reflecting the RF signal from the controllable-variable-impedance element to a fourth terminal of the directional device.
2. The method of claim 1, comprising:
establishing a corresponding relationship between a group of at least two control-parameters and an error vector in a look up table for each selected frequency in a list of selected frequencies.
3. The method of claim 2, wherein the establishing a corresponding relationship between a group of at least two control-parameters and an error vector comprises:
selecting the group of at least two control-parameters corresponding to the error vector to minimize the spurious RF signal received from the antenna when the impedance of the controllable-variable-impedance element is set with the group of at least two control-parameters.
4. The method of claim 1, wherein the controllable-variable-impedance element comprises a controllable-variable-attenuation element and a controllable-variable-phase element, and wherein the setting the impedance of a controllable-variable-impedance element comprises:
setting an attenuation of the controllable-variable-attenuation element with at least one attenuation control-parameter; and
setting a phase delay of the controllable-variable-phase element with at least one phase control-parameter.
5. An apparatus comprising:
a directional device having a first terminal, a second terminal, a third terminal, and a fourth terminal;
an antenna coupled to the second terminal of the directional device for transmitting an outgoing RF signal and receiving a RF signal reflected by an RF tag and a spurious RF signal;
a demodulator generating a demodulated vector signal from the RF signal and the spurious RF signal received by the antenna;
a filter generating an error vector in response to the demodulated vector signal received from the demodulator;
a memory circuit operable to output a group of at least two control-parameters in response to the error vector received from the filter, and wherein the memory circuit includes a look up table containing a frequency dependent relationship between the group of at least two control-parameters and the error vector; and
a controllable-variable-impedance element coupled to the fourth terminal of the directional device, the controllable-variable-impedance element having the impedance thereof controllable with the group of at least two control-parameters received from the memory circuit.
6. The apparatus of claim 5, further comprising:
an RF amplifier coupled to the first terminal of the directional device.
7. The apparatus of claim 5, further comprising:
a low noise amplifier coupled to the third terminal of the directional device.
8. The apparatus of claim 5, wherein the controllable-variable-impedance element comprises:
a controllable-variable-attenuation element receiving at least one attenuation control-parameter from the memory circuit to control an attenuation of the controllable-variable-attenuation element; and
a controllable-variable-phase element receiving at least one phase control-parameter from the memory circuit to control a phase delay of the controllable-variable-phase element.
9. The apparatus of claim 8, wherein the controllable-variable-phase element comprises a fine controllable-variable-phase element and a coarse controllable-variable-phase element.
10. The apparatus of claim 5, wherein the controllable-variable-impedance element comprises:
a controllable-variable-attenuation element having an attenuation thereof controllable with the memory circuit; and
a controllable-variable-phase element having a phase delay thereof controllable with the memory circuit.
11. An apparatus comprising:
a directional device having a first terminal, a second terminal, a third terminal, and a fourth terminal;
a receiver receiving a RF signal from the third terminal of the directional device;
a demodulator generating a demodulated vector signal from a RF signal related to the RF signal received from the receiver;
a memory circuit coupled to the demodulator, the memory circuit receiving an error vector and outputting a group of at least two control-parameters, the memory circuit including a look up table containing a frequency dependent relationship between the group of at least two control-parameters and the error vector for each selected frequency in a list of selected frequencies; and
a controllable-variable-impedance element coupled to the fourth terminal of the directional device and receiving the group of at least two control-parameters from the memory circuit to control the impedance of the controllable-variable-impedance element.
12. The apparatus of claim 11, further comprising:
a filter coupled between the demodulator and the memory circuit, the filter receiving the demodulated vector signal from the demodulator and outputting the error vector to the memory circuit.
13. The apparatus of claim 11, further comprising:
an RF amplifier coupled to the first terminal of the directional device.
14. The apparatus of claim 11, further comprising:
an antenna coupled to the second terminal of the directional device.
15. The apparatus of claim 11, wherein the controllable-variable-impedance element comprises:
a controllable-variable-attenuation element receiving at least one attenuation control-parameter from the memory circuit to control an attenuation of the controllable-variable-attenuation element; and
a controllable-variable-phase element receiving at least one phase control-parameter from the memory circuit to control a phase delay of the controllable-variable-phase element.
16. The apparatus of claim 15, wherein the controllable-variable-phase element comprises a fine controllable-variable-phase element and a coarse controllable-variable-phase element.
17. The apparatus of claim 11, wherein the controllable-variable-impedance element comprises:
a controllable-variable-attenuation element having an attenuation thereof controllable with the memory circuit; and
a controllable-variable-phase element having a phase delay thereof controllable with the memory circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A radio frequency identification (RFID) device comprising:
an analog block configured to receive a radio frequency signal so as to output an operating command signal;
a digital block configured to generate and output an address and an operation adjusting signal in response to the operating command signal, output a response signal to the analog block, and generate a flag data corresponding to a data processing state and value; and
a memory block configured to read and write a data in a nonvolatile ferroelectric capacitor in response to the operation adjusting signal,
wherein the memory block comprises a memory unit configured to store the flag data so as to output the flag data to the digital block.
2. The RFID device according to claim 1,
wherein the memory unit stores the flag data for a given time when a power voltage supplied to the digital block drops below a critical voltage.
3. The RFID device according to claim 1,
wherein the memory unit comprises:
a first data storage unit configured to store the flag data; and
an output driving unit configured to drive an output signal of the first data storage unit.
4. The RFID device according to claim 3,
wherein the first data storage unit comprises:
a first transmission element configured to transmit the flag data to a first storage node;
a second transmission element configured to transmit an inversion data of the flag data to a second storage node;
a first storage element configured to charge potentials at the first storage node and the second storage node; and
a first latch unit configured to latch the potentials at the first storage node and at the second storage node.
5. The RFID device according to claim 4,
wherein the first transmission element comprises a first NMOS transistor which is connected between a flag data receiving terminal and the first storage node and has a gate to receive the flag data.
6. The RFID device according to claim 4,
wherein the second transmission element comprises a second NMOS transistor connected between an inversion data receiving terminal and the second storage node in which the second NMOS transistor has a gate to receive the inversion data.
7. The RFID device according to claim 4,
wherein the first storage element comprises a first ferroelectric capacitor connected between the first and the second storage node.
8. The RFID device according to claim 4,
wherein the first latch unit comprises:
a third NMOS transistor connected between the first storage node and a ground voltage terminal, wherein the gate of the third NMOS transistor is connected to the second storage node; and
a fourth NMOS transistor connected between the second storage node and the ground voltage terminal, wherein the gate of the fourth NMOS transistor is connected to the first storage node, and wherein the gates of the third and fourth NMOS transistors being cross-coupled to each other.
9. The RFID device according to claim 4,
wherein the memory unit further comprises a first comparator configured to compare the flag data with the inversion data so as to output a write enable signal to the first and second transmission elements.
10. The RFID device according to claim 9,
wherein the first comparator comprises an XOR (exclusive OR) gate.
11. The RFID device according to claim 9,
wherein the first storage element comprises a second ferroelectric capacitor connected between the first storage node and the ground voltage terminal.
12. The RFID device according to claim 9,
wherein the first storage element comprises a third ferroelectric capacitor connected between the second storage node and the ground voltage terminal.
13. The RFID device according to claim 3,
wherein the output driving unit comprises:
a first driving unit configured to pull up the output signal of the first data storage unit; and
a second driving unit configured to pull down the output signal of the first data storage unit.
14. The RFID device according to claim 13,
wherein the first driving unit comprises:
a first PMOS transistor connected between a power voltage terminal and a first output terminal, wherein the gate of the first PMOS transistor is connected to a second output terminal; and
a second PMOS transistors connected between the power voltage terminal and the second output terminal, wherein the gate of the second PMOS transistor is connected to the first output terminal, and wherein the first and second PMOS transistor gates are cross-coupled to each other.
15. The RFID device according to claim 13,
wherein the second driving unit comprises:
a fifth NMOS transistor connected between the first output terminal and the ground voltage terminal, wherein the gate of the fifth NMOS transistor is connected to the second storage node; and
a sixth NMOS transistor connected between the second output terminal and the ground voltage terminal, wherein the gate of the sixth NMOS transistor is connected to the first storage node.
16. The RFID device according to claim 1,
wherein the memory unit comprises:
a second data storage unit configured to store the flag data; and
a second latch unit configured to latch an output signal of the second data storage unit.
17. The RFID device according to claim 16,
wherein the second data storage unit comprises:
a third transmission element configured to transmit the flag data to a first output node;
a fourth transmission element configured to transmit an inversion data of the flag data to a second output node;
a second storage element configured to charge potentials at the first and the second output nodes; and
a third latch unit configured to latch the charged potentials at the first and second output nodes.
18. The RFID device according to claim 17,
wherein the third transmission element comprises a seventh NMOS transistor connected between a flag data receiving terminal and the first output node and the seventh NMOS transistor having a gate to receive the flag data.
19. The RFID device according to claim 17,
wherein the fourth transmission element comprises an eighth NMOS transistor connected between the inversion data of the flag data receiving terminal and the second output node and the eighth NMOS transistor having a gate to receive the inversion data of the flag data.
20. The RFID device according to claim 17,
wherein the second storage element comprises a fourth ferroelectric capacitor connected between the first output node and the second output node.
21. The RFID device according to claim 17,
wherein the third latch unit comprises:
a ninth NMOS transistor connected between the first output node and the ground voltage terminal, wherein the gate of the ninth NMOS transistor is connected to a second output node; and
a tenth NMOS transistor connected between the second output node and the ground voltage terminal, wherein the gate of the tenth NMOS transistor is connected to the first output node, and wherein the gates of the ninth and tenth NMOS transistors are cross-coupled to each other.
22. The RFID device according to claim 17,
wherein the memory unit further comprises a second comparator configured to compare the flag data with the inversion data of the flag data so as to output a write enable signal to the third and the fourth transmission elements.
23. The RFID device according to claim 22, wherein the second comparator comprises an XOR (exclusive OR) gate.
24. The RFID device according to claim 22, wherein the second storage element comprises a fifth ferroelectric capacitor which is connected between the first output node and the ground voltage terminal.
25. The RFID device according to claim 22, wherein the second storage element comprises a sixth ferroelectric capacitor which is connected between the second output node and the ground voltage terminal.