1. A semiconductor structure comprising:
buried conductors formed in vertical structures and inducing a metal silicide; and
a barrier layer contacting with the metal silicide and containing germanium (Ge).
2. The semiconductor structure according to claim 1, wherein the barrier layer comprises silicon germanium (SiGe).
3. The semiconductor structure according to claim 2, wherein a content of germanium in the barrier layer is at least approximately 30%.
4. A semiconductor device comprising:
semiconductor bodies formed substantially perpendicular to a semiconductor substrate;
buried bit lines formed in the semiconductor bodies and including a metal silicide; and
barrier layers formed under and over the buried bit lines and containing germanium.
5. The semiconductor device according to claim 4, wherein each of the barrier layers comprises silicon germanium.
6. The semiconductor device according to claim 5, wherein a content of germanium in each of the barrier layers is at least approximately 30%.
7. The semiconductor device according to claim 4, wherein the metal silicide comprises a cobalt silicide.
8. The semiconductor device according to claim 4, further comprising:
semiconductor pillars formed over the semiconductor bodies and including channel regions of vertical channel transistors; and
storages connected to upper portions of the semiconductor pillars.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for filling of a shallow trench isolation, said method comprises:
providing a wafer which comprises a semiconductor substrate;
forming a pad oxide layer on said semiconductor substrate;
forming a first silicon nitride layer on said pad oxide layer;
etching part of said first silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form a trench;
forming a thermal oxide layer on a surface of said trench;
forming a second silicon nitride layer on said thermal oxide layer and said first silicon nitride layer;
anisotropic etching said second silicon nitride layer and said thermal oxide layer until showing said semiconductor substrate; and
forming a ozone-TEOS layer inside said trench.
2. The method according to claim 1, wherein said anisotropic etching method is a reactive ion etching method.
3. A method for filling of a shallow trench isolation, said method comprises:
providing a wafer which comprises a semiconductor substrate;
forming a pad oxide layer on said semiconductor substrate;
forming a first silicon nitride layer on said pad oxide layer;
etching part of said first silicon nitride layer, said pad oxide layer, and said semiconductor substrate to form a trench;
forming a thermal oxide layer on a surface of said trench;
forming a second silicon nitride layer on said thermal oxide layer and said first silicon nitride layer;
etching said second silicon nitride layer and said thermal oxide layer until showing said semiconductor substrate by using a reactive ion etching;
forming a ozone-TEOS layer inside said trench,
forming a oxide layer on a contacting surface which is located between said ozone-TEOS layer and said semiconductor substrate and on said bottom of said trench; and
polishing said ozone-TEOS layer until showing said first silicon nitride layer.
4. The method according to claim 3, wherein a width of said trench is about 0.10 to 0.24 microns.
5. The method according to claim 3, wherein a depth of said trench is about 3000 to 4000 angstroms.
6. The method according to claim 3, wherein said polishing method is a chemical mechanical polishing method.
7. The method according to claim 3, wherein a thickness of said oxide layer is about 90 to 110 angstroms.