1. A data storage device comprising:
a first data storage medium including a partition dedicated to store a log indicating operational state information of the data storage device; and
a controller configured to selectively store the operational state information to the partition in a first-in first-out (FIFO) order.
2. The data storage device of claim 1 further comprising:
an interface connectable to a data bus; and
a second data storage medium adapted to store data received from the data bus;
wherein the first data storage medium comprises a non-volatile solid state data storage medium.
3. The data storage device of claim 2 wherein the operational state information comprises commands received over the interface, data associated with the commands, performance data associated with the data storage device, and environmental data associated with the data storage device.
4. The data storage device of claim 3 wherein the performance data associated with the data storage device comprises power mode state data, interface drive circuit data, spindle motor data, actuator position data, readwrite head selection data, readwrite channel settings data, and preamplifier settings data.
5. The data storage device of claim 3 further comprising at least one environmental sensor to monitor environmental data associated with the data storage device.
6. The data storage device of claim 5 wherein the environmental data associated with the data storage device comprises temperature data, vibration data, and shock detection data.
7. The data storage device of claim 1 wherein the controller is adapted to selectively store the operational information when a trigger event occurs.
8. The data storage device of claim 7 wherein the trigger event is receiving a command or data from the data bus, executing a command, detecting a read or write error, detecting a data error, completion of an executed command, inactivity for a certain time, transition of the data storage device from a first state to a second state, or expiration of a timer.
9. A data storage device comprising:
an interface to receive data and commands;
a first data storage medium to store the data received at the interface;
a second data storage medium including a failure partition comprising a storage device failure log; and
a controller adapted to store state information associated with the data storage device, the data, and the commands in the storage device failure log.
10. The data storage device of claim 9 wherein the controller is adapted to control access to the first data storage medium and the second data storage medium.
11. The data storage device of claim 9 wherein the failure partition comprises a reserved and addressable portion of the second data storage medium and the controller is configured to selectively store the state information to the storage device failure log in a first-in first-out (FIFO) order.
12. The data storage device of claim 9 wherein the first data storage medium comprises a disc data storage medium and wherein the second data storage medium comprises a non-volatile solid-state data storage medium.
13. The data storage device of claim 9 wherein the state information comprises commands received over the interface, data associated with the commands, performance data associated with the data storage device, and environmental data associated with the data storage device.
14. The data storage device of claim 13 wherein the state information comprises data related to recovery actions taken to recover from a failure event.
15. A data storage device comprising:
a solid-state data storage medium including a failure log partition comprising a storage device failure log; and
a controller configured to store operational state information of the data storage device in the storage device failure log, the operational state information including commands received from a host device, environmental data from at least one environmental sensor, and state information related to operating conditions of the data storage device.
16. The data storage device of claim 15 wherein the failure log partition comprises a reserved and addressable portion of the solid-state data storage medium and the controller is configured to selectively store the operational state information to the storage device failure log in a first-in first-out (FIFO) order.
17. The data storage device of claim 15 further comprising a second data storage medium adapted to store user data, wherein the controller is adapted to control readwrite access to the second data storage medium.
18. The data storage device of claim 15 further comprising a second data storage medium adapted to store user data and a second controller to control readwrite access to the second data storage medium, wherein the operational state information comprises state information related to the second controller.
19. The data storage device of claim 15, further comprising:
a host interface responsive to a host system to receive commands and user data; and
at least one firmware sensor to generate state information related to at least one circuit in the data storage device.
20. The data storage device of claim 15 further comprising an interface to allow access to the storage device failure log from external to the data storage device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a cell array; and
a plurality of process failure detection circuits each having a layout pattern substantially identical to that of a cell of the cell array in a dummy region arranged around the cell array.
2. The semiconductor device according to claim 1, wherein each of the process failure detection circuits in the dummy region comprises:
a dummy pattern that equalizes a degree of densitysparsity of a peripheral part of the cell array with that of a central part of the cell array.
3. The semiconductor device according to claim 1, wherein the plurality of the process failure detection circuits comprise:
a process failure detection circuit having a layout pattern formed with a stricter pattern margin in at least one manufacturing process, compared with the layout pattern of the cell of the cell array.
4. The semiconductor device according to claim 1, wherein the plurality of the process failure detection circuits comprise:
a plurality types of the process failure detection circuits, each type of the plurality types of the process failure detection circuits having a layout pattern formed with a stricter pattern margin in a different manufacturing process, compared with the layout pattern of the cell of the cell array.
5. The semiconductor device according to claim 4, wherein the plurality types of the process failure detection circuits comprise:
a wiring process failure detection circuit including a stricter wiring pattern compared with the wiring pattern of the cell of the cell array, said wiring pattern including any of wiring and via patterns; and
a base layer process failure detection circuit including a stricter base layer pattern compared with the base layer pattern of the cell of the cell array, said base layer pattern including any of gate, contact, and field patterns.
6. The semiconductor device according to claim 3, wherein the process failure detection circuits comprise:
a first process failure detection circuit having a layout pattern formed by increasing a first pattern size toward an upper limit and decreasing a second pattern size toward a lower limit; and
a second process failure detection circuit having a layout pattern formed by decreasing the first pattern size toward a lower limit and increasing the second pattern size toward an upper limit, wherein the sum of the first pattern size and the second pattern size is fixed.
7. The semiconductor device according to claim 1, wherein the cell array is a memory cell array, and each of the plurality of process failure detection circuits shares a readwrite circuit with the memory cell array.
8. A method of manufacturing a semiconductor device, the semiconductor device comprising a cell array and a plurality of types of process failure detection circuits, each having a layout pattern substantially identical to that of a cell of the cell array in a dummy region around the cell array, each type of the process failure detection circuit having a layout pattern formed with a stricter pattern margin in a different manufacturing process of the semiconductor device, compared with the layout pattern of the cell of the cell array, the method comprising:
carrying out a surface inspection of a first process by using a first type process failure detection circuit of the plurality types of the process failure detection circuit, the first type process failure detection circuit having a layout pattern formed with a stricter pattern margin in the first process pattern, the first process being a one process in a wafer-level manufacturing processes of the semiconductor device;
providing feedback about a manufacturing condition to the first process when a problem is found in the surface inspection of the first process;
carrying out a function test on the plurality of types of process failure detection circuits after completion of the wafer-level manufacturing processes;
determining a problematic manufacturing process by using a result of the function test on the plurality of types of process failure detection circuits when a problem is found in the function test; and
providing feedback about manufacturing condition of the problematic manufacturing process.
9. The method according to claim 8, wherein determining a problematic manufacturing process comprises:
analyzing a position of a failure semiconductor device determined by the function test of a total function of the semiconductor device found on the wafer, the position of the failure for each type of the process failure detection circuit found on the wafer, and failure occurrence frequency; and
determining the problematic manufacturing processes based on a result of the analyzing.
10. The method according to claim 8, wherein the cell array is a memory cell array, and a function test of the process failure detection circuit is carried out by performing readwrite access to the process failure detection circuit via the memory cell array.