1. An information handling system comprising:
a plurality of simultaneous multi-threading (SMT) processors;
a memory accessible by the processors;
a plurality of software threads and a plurality of run queues stored in the memory, wherein each of the run queues corresponds to one of the SMT processors;
a thread scheduling tool for scheduling threads among the plurality of SMT processors, the thread scheduling tool comprising software code effective to:
determine that a first thread from the plurality of software threads that is in a first run queue selected from the plurality of run queues is a poor performing thread, wherein the first run queue corresponds to a first SMT processor selected from the plurality of SMT processors, wherein the software code that performs the determination includes software code effective to:
execute a plurality of threads listed in the first run queue, including the first thread, on the first SMT processor, the software code that performs the execution further including software code effective to:
retrieve a number of cycles value for each thread indicating the number of cycles that occurred while each thread was executing;
retrieve a number of instructions value for each thread indicating the number of instructions that were executed while each thread was executing;
divide each number of cycles value by its corresponding number of instructions value, the dividing resulting in a cycles per instruction (CPI) value; and
record the CPI value for each thread in the first queue; and
identify the first thread as having a CPI value worse than a plurality of the other threads listed in the first run queue; and
in response to the determination, the software code is effective to:
write a first identifier corresponding to the first thread to a second run queue, wherein the second run queue corresponds to a second SMT processor selected from the plurality of SMT processors; and
remove the first identifier from the first run queue.
2. The information handling system as described in claim 1 wherein the software code is further effective to:
determine that a second thread in the second run queue is another poor performing thread;
in response to the determination regarding the second thread:
write a second identifier corresponding to the second thread to the first run queue; and
remove the second identifier from the second run queue.
3. The information handling system as described in claim 1 wherein the software code is further effective to:
determine whether each thread was previously moved from one of a plurality of SMT processors’ run queues to the first SMT processor’s run queue.
4. The information handling system as described in claim 3 wherein the software code is further effective to:
determine that the CPI of the first thread has degraded since being moved to the first SMT processor’s run queue.
5. The information handling system as described in claim 1 wherein the software code is further effective to:
record the first thread’s identifier, the first thread’s CPI, and a timestamp to a previously swapped data structure.
6. The information handling system as described in claim 5 wherein the timestamp corresponds to a time selected from the group consisting of a time that the first thread’s CPI was calculated, and a time that the first thread’s identifier was moved from the first run queue to the second run queue.
7. The information handling system as described in claim 1 wherein the software code is further effective to:
average the CPI value for each of the plurality of threads with one or more previous CPI values previously calculated for each of the threads, wherein the recorded CPI value includes the average CPI value for each thread.
8. The information handling system as described in claim 1 wherein the
software code is further effective to:
skip one or more worse performing threads in comparison to the first thread in response to determining that each of the worse performing threads has previously been moved to the first SMT processor’s run queue and each has improved in performance since being moved; and
identify the first thread after skipping the worse performing threads.
9. A computer program product stored on a computer operable media for scheduling threads for a plurality of simultaneous multi-threading (SMT) processors, said computer program product comprising:
means for determining that a first thread in a first run queue is a poor performing thread, wherein the first run queue corresponds to a first SMT processor, wherein the means for determining further includes:
means for executing a plurality of threads listed in the first run queue, including the first thread, on the first SMT processor, the means for executing further including:
means for retrieving a number of cycles value for each thread indicating the number of cycles that occurred while each thread was execution;
means for retrieving a number of instructions value for each thread indicating the number of instructions that were executed while each thread was executing;
means for dividing each number of cycles value by its corresponding number of instructions value, the dividing resulting in a cycles per instruction (CPI) value; and
means for recording the CPI value for each thread in the first queue; and
means for identifying the first thread as having a CPI value worse than a plurality of the other threads listed in the first run queue; and
in response to the determination:
means for writing a first identifier corresponding to the first thread to a second run queue, wherein the second run queue corresponds to a second SMT processor; and
means for removing the first identifier from the first run queue.
10. The computer program product as described in claim 9 further comprising:
means for determining that a second thread in the second run queue is another poor performing thread;
in response to the determination regarding the second thread:
means for writing a second identifier corresponding to the second thread to the first run queue; and means for removing the second identifier from the second run queue.
11. The computer program product as described in claim 9 further comprising:
means for determining whether each thread was previously moved from one of a plurality of SMT processors’ run queues to the first SMT processor’s run queue.
12. The computer program product as described in claim 11 further comprising:
means for determining that the CPI of the first thread has degraded since being moved to the first SMT processor’s run queue.
13. The computer program product as described in claim 9 further comprising:
means for recording the first thread’s identifier, the first thread’s CPI, and a timestamp to a previously swapped data structure.
14. The computer program product as described in claim 13 wherein the timestamp corresponds to a time selected from the group consisting of a time that the first thread’s CPI was calculated, and a time that the first thread’s identifier was moved from the first run queue to the second run queue.
15. The computer program product as described in claim 9 further comprising:
means for averaging the CPI value for each of the plurality of threads with one or more previous CPI values previously calculated for each of the threads, wherein the recorded CPI value includes the average CPI value for each thread.
16. The computer program product as described in claim 9 further comprising:
means for skipping one or more worse performing threads in comparison to the first thread in response to determining that each of the worse performing threads has previously been moved to the first SMT processor’s run queue and each has improved in performance since being moved; and
means for identifying the first thread after skipping the worse performing threads.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a silicon solar cell, comprising:
providing a carrier plate;
applying a first contact pattern to the carrier plate, the first contact pattern comprising a set of first laminar contacts;
applying plurality of preformed, integral, and individual silicon slices to the first contact pattern in a pick-and-place manner such that the silicon slices as preformed are picked up and placed on the first contact pattern, the silicon slices being preformed in that the silicon slices do not undergo any further processing thereof after placement on the first contact pattern, the silicon slices being integral in that each silicon slice is integrally complete prior to placement on the first contact pattern, the silicon slices being individual in that each silicon slice is not separated or cut into more than one silicon slice after placement on the first contact pattern, wherein each first laminar contact of the set of first laminar contacts is in direct physical spatial laminar contact with no more than two silicon slices; and,
applying a second contact pattern to the plurality of silicon slices, wherein the second contact pattern comprises a set of second laminar contacts, and wherein each second laminar contact of the set of second laminar contacts is in direct physical spatial laminar contact with no more than two silicon slices.
2. The method of claim 1, wherein:
each first laminar contact of the set of first laminar contacts is in spatial laminar contact with exactly two silicon slices, and
each second laminar contact of the set of second laminar contacts is in spatial laminar contact with exactly two silicon slices.
3. The method of claim 1, wherein each silicon slice is in spatial laminar contact with exactly one first laminar contact and one second laminar contact.
4. The method of claim 1, further comprising one or more of passivating and anti-reflective coating one or more of the carrier plate and the silicon slices.
5. The method of claim 1, further comprising one or more of adhering the silicon slices to the first laminar contacts and adhering the silicon slices to the second laminar contacts.
6. The method of claim 5, wherein one or more of:
the adhesion of the silicon slices to the first laminar contacts is performed by applying a first contact glue to the set of first laminar contacts or the silicon slices, the first contact glue adhering the silicon slices to the first laminar contacts, and
the adhesion of the silicon slices to the second laminar contacts is performed by applying a second contact glue to the set of second laminar contacts or the silicon slices, the second contact glue adhering the silicon slices to the second laminar contacts.
7. The method of claim 5, wherein one or more of the adhesion of the silicon slices to the first laminar contacts is performed by anodic bonding techniques, and the adhesion of the silicon slices to the second laminar contacts is performed by anodic bonding techniques.
8. The method of claim 1, wherein the first or the second contact pattern is applied to the carrier plate by printing or by lithography.
9. The method of claim 8, wherein the printing is a screen printing process, or wherein the printing is performed using a hard mask.
10. The method of claim 9, wherein the printing comprises:
covering the carrier plate with a first hard mask, the first hard mask comprising a pattern of first openings, the first openings uncovering the carrier plate at areas designated for the first contact pattern;
depositing a masking material through the first hard mask on the carrier plate;
removing the first hard mask;
depositing a conductive material on the carrier plate; and,
removing the masking material from the carrier plate,
wherein the remaining conductive material constitutes the first contact pattern.
11. The method of claim 10, wherein the printing further comprises:
covering the plurality of silicon slices with a second hard mask, the second hard mask comprising a pattern of second openings, the second openings uncovering the plurality of silicon slices at areas designated for the second contact pattern;
depositing a masking material through the second hard mask on the carrier plate;
removing the second hard mask;
depositing a conductive material on the plurality of silicon slices; and,
removing the masking material from the carrier plate,
wherein the remaining conductive material constitutes the second contact pattern.
12. The method of claim 9, wherein the hard mask is provided by using soft-stamping techniques.
13. The method of claim 1, further comprising applying a filler material to the silicon slices, wherein the filler material fills the gaps between adjacent silicon slices, and wherein the filler material is electrically isolating.