1. A signal processing circuit extracting a signal superimposed on a reference signal varying in level at a given frequency, the superimposed signal being inserted into the reference signal at given positions of a given level thereof and having a peak level higher than a level of the reference signal by a value greater than a given value, the signal processing circuit comprising:
a first pulse generation part generating a first binary signal by binarizing a composite signal of the reference signal and the superimposed signal by using a given reference level as a threshold value;
a noise elimination part eliminating noise from the first binary signal by using a cumulative length of time of each of polarities of the first binary signal;
a second pulse generation part generating a second binary signal by binarizing the composite signal by using, as a threshold value, a level higher than the level of the reference signal by a value smaller than or equal to the given value; and
a gate part outputting the second binary signal based on a signal output from said noise elimination part.
2. The signal processing circuit as claimed in claim 1, wherein said noise elimination part eliminates the noise from and delays, for a given period of time, the first binary signal.
3. The signal processing circuit as claimed in claim 2, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
4. The signal processing circuit as claimed in claim 3, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
5. The signal processing circuit as claimed in claim 1, wherein said noise elimination part eliminates the noise from and changes a pulse width of the first binary signal.
6. The signal processing circuit as claimed in claim 5, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
7. The signal processing circuit as claimed in claim 6, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
8. The signal processing circuit as claimed in claim 1, wherein said noise elimination part eliminates the noise from, delays, for a given period of time, and changes a pulse width of the first binary signal.
9. The signal processing circuit as claimed in claim 8, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
10. The signal processing circuit as claimed in claim 9, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
11. The signal processing circuit as claimed in claim 1, wherein said noise elimination part comprises:
a gate part for noise elimination that outputs given clock pulses based on the first binary signal;
a count part for noise elimination that counts the given clock pulses; and
a clear part for noise elimination that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
12. The signal processing circuit as claimed in claim 11, wherein:
said gate part for noise elimination comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the first binary signal;
said count part for noise elimination comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for noise elimination switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
13. The signal processing circuit as claimed in claim 1, wherein said gate part outputs the second binary signal only during a period of one of polarities of the signal output from said noise elimination part.
14. A signal processing circuit extracting a signal superimposed on a reference signal varying in level at a given frequency, the superimposed signal being inserted into the reference signal at given positions of a given level thereof and having a peak level higher than a peak level of the reference signal, the signal processing circuit comprising:
a first pulse generation part generating a first binary signal by binarizing a composite signal of the reference signal and the superimposed signal by using a given reference level as a threshold value;
a noise elimination part eliminating noise from the first binary signal by using a cumulative length of time of each of polarities of the first binary signal;
a second pulse generation part generating a second binary signal by binarizing the composite signal by using, as a threshold value, a level higher than or equal to the peak level of the reference signal; and
a gate part outputting the second binary signal based on a signal output from said noise elimination part.
15. The signal processing circuit as claimed in claim 14, wherein said noise elimination part eliminates the noise from and delays, for a given period of time, the first binary signal.
16. The signal processing circuit as claimed in claim 15, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
17. The signal processing circuit as claimed in claim 16, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
18. The signal processing circuit as claimed in claim 14, wherein said noise elimination part eliminates the noise from and changes a pulse width of the first binary signal.
19. The signal processing circuit as claimed in claim 18, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
20. The signal processing circuit as claimed in claim 19, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
21. The signal processing circuit as claimed in claim 14, wherein said noise elimination part eliminates the noise from, delays, for a given period of time, and changes a pulse width of the first binary signal.
22. The signal processing circuit as claimed in claim 21, wherein said noise elimination part comprises:
a gate part for delaying that outputs given clock pulses based on the noise-eliminated first binary signal;
a count part for delaying that counts the given clock pulses; and
a clear part for delaying that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
23. The signal processing circuit as claimed in claim 22, wherein:
said gate part for delaying comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the noise-eliminated first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the noise-eliminated first binary signal;
said count part for delaying comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for delaying switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
24. The signal processing circuit as claimed in claim 14, wherein said noise elimination part comprises:
a gate part for noise elimination that outputs given clock pulses based on the first binary signal;
a count part for noise elimination that counts the given clock pulses; and
a clear part for noise elimination that switches a level of an output thereof between first and second values based on a count value of said count part and clears the count value based on the level of the output.
25. The signal processing circuit as claimed in claim 24, wherein:
said gate part for noise elimination comprises:
a first gate part outputting the given clock pulses only during a period of a first polarity of the first binary signal; and
a second gate part outputting the given clock pulses only during a period of a second polarity of the first binary signal;
said count part for noise elimination comprises:
a first counter counting the given clock pulses output from said first gate part; and
a second counter counting the given clock pulses output from said second gate part; and
said clear part for noise elimination switches the level of the output thereof to the first value and clears a count value of said first counter when the count value of said first counter reaches a first count value, and switches the level of the output thereof to the second value and clears a count value of said second counter when the count value of said second counter reaches a second count value.
26. The signal processing circuit as claimed in claim 14, wherein said gate part outputs the second binary signal only during a period of one of polarities of the signal output from said noise elimination part.
27. A method of extracting a signal superimposed on a reference signal varying in level at a given frequency, the superimposed signal being inserted into the reference signal at given positions of a given level thereof and having a peak level higher than a level of the reference signal by a value greater than a given value, the method comprising the steps of:
(a) generating a first binary signal by binarizing a composite signal of the reference signal and the superimposed signal by using a given reference level as a threshold value;
(b) eliminating noise from the first binary signal by using a cumulative length of time of each of polarities of the first binary signal;
(c) generating a second binary signal by binarizing the composite signal by using, as a threshold value, a level higher than the level of the reference signal by a value smaller than or equal to the given value; and
(d) outputting the second binary signal based on a signal generated by said step (b).
28. The method as claimed in claim 27, wherein said step (b) eliminates the noise from and delays, for a given period of time, the first binary signal.
29. The method as claimed in claim 27, wherein said step (b) eliminates the noise from and changes a pulse width of the first binary signal.
30. The method as claimed in claim 27, wherein said step (b) eliminates the noise from, delays, for a given period of time, and changes a pulse width of the first binary signal.
31. The method as claimed in claim 27, wherein said step (d) outputs the second binary signal only during a period of one of polarities of the signal generated by said step (b).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A body supporting tool for a bed comprising:
a guide rail releasably fixed to a frame of said bed;
a slide housing movable relative to said guide rail while guided by said guide rail;
a turning support turnably held by said slide housing at a base end portion thereof and having an operating member on an upper end portion thereof;
a slide housing movement control mechanism provided within said slide housing for switching states of said slide housing between a slide housing moving state in which said slide housing is allowed to move relative to said guide rail and a slide housing fixing state in which said slide housing is not allowed to move relative to said guide rail;
a support turning motion converting mechanism for causing said slide housing movement control mechanism to switch said states of said slide housing from said slide housing moving state to said slide housing fixing state when said turning support is turned in a set direction by a set angle, and from said slide housing fixing state to said slide housing moving state when said turning support is turned in a direction opposite to said set direction by said set angle; and
an abutment plate swingably supported around said turning support by said turning support, moving forward and backward along said guide rail together with said slide housing when said slide housing moves forward and backward along said guide rail, and supporting a body of a person lying on said bed while abutting said body.
2. A body supporting tool for a bed according to claim 1, wherein said slide housing movement control mechanism includes fixed engaging members and movable engaging members engaging with said fixed engaging members;
said fixed engaging members extend in a longitudinal direction of said guide rail integrally with said guide rail; and
said movable engaging members are arranged within said slide housing in such a manner that said movable engaging members move along said guide rail together with said fixed engaging members on said guide rail and are set in a slide housing moving position where movement of said slide housing is permitted as said movable engaging members evacuate from an engaging position where said movable engaging members are engageable with said fixed engaging members on said guide rail and in a slide housing fixing position where movement of said slide housing is prohibited as said movable engaging members engage with said fixed engaging members on said guide rail.
3. A body supporting tool for a bed according to claim 1 or 2, wherein said support turning motion converting mechanism has a cam mechanism at a base end portion of said turning support in a manner coupled to interlock with turning movement of said turning support, and said cam mechanism causes said slide housing movement control mechanism to switch said states from said slide housing moving state to said slide housing fixing state when said turning support is turned in a set direction by a set angle, and from said slide housing fixing state to said slide housing moving state when said turning support is turned in a direction opposite to said set direction by said set angle.