1. A frequency synthesizer comprising:
a mixer which generates a frequency synthesized signal whose frequency is a synthesis of first high frequency I and Q signals and second high frequency I and Q signals;
a selector which selects and outputs one of the I signal of the first high frequency and the frequency synthesized signal; and
an oscillator which receives an output signal of the selector and generates a first local signal and a second local signal having a quadrature-phase with each other based on the output signal of the selector.
2. The frequency synthesizer of claim 1, wherein each of the first and second local signal has a frequency identical to a frequency of the output signal of the selector.
3. The frequency synthesizer of claim 1, wherein the first and second local signal of the oscillator each has a frequency which is one half a frequency of the output signal of the selector.
4. The frequency synthesizer of claim 1, wherein the frequency synthesized signal is an addition of the first high frequency I and Q signals and the second high frequency I and Q signals.
5. The frequency synthesizer of claim 1, wherein the frequency synthesized signal is a difference between the first high frequency I and Q signals and the second high frequency I and Q signals.
6. The frequency synthesizer of claim 1, wherein the oscillator comprises:
a first oscillator which generates a first differential signal set from a second differential signal set input via first positive and negative input terminals; and
a second oscillator which receives positive and negative signals of a third differential signal set for frequency locking via second positive and negative input terminals, respectively, receives positive and negative signals of the first differential signal set via third positive and negative input terminals, respectively, and generates the second differential signal set based on the positive and negative signals of the third differential signal set and the positive and negative signals of the first differential signal set.
7. The frequency synthesizer of claim 6, wherein the positive signal of the second differential signal is input to the first negative input terminal of the first oscillator, and the negative signal of the second differential signal is input to the first positive input terminal of the first oscillator.
8. The frequency synthesizer of claim 7, wherein:
the first oscillator comprises a plurality of metal-oxide semiconductor field effect transistors (MOSFETs) having gate terminals coupled between a first load circuit and a first current source, as the first positive and negative input terminals, and
the second oscillator comprises a plurality of MOSFETs having gate terminals coupled between second load circuit and second current source, as the second positive and negative input terminals and the third positive and negative input terminals.
9. A frequency synthesizing method comprising:
generating a frequency synthesized signal whose frequency is a synthesis of first high frequency I and Q signals and second high frequency I and Q signals;
selecting one of the first high frequency I signal and the frequency synthesized signal and outputting a selected signal;
inputting the selected signal into an oscillator; and
generating a first local signal and a second local signal having a quadrature-phase with each other based on the selected signal.
10. The frequency synthesizing method of claim 9, wherein each of the first and second local signal has a frequency identical to a frequency of the selected signal.
11. The frequency synthesizing method of claim 9, wherein the first and second local signal each has a frequency which is one half a frequency of the selected signal.
12. The frequency synthesizing method of claim 9, wherein the frequency synthesized signal is an addition of the first high frequency I and Q signals and the second high frequency I and Q signals.
13. The frequency synthesizing method of claim 9, wherein the frequency synthesized signal is a difference between the first high frequency I and Q signals and the second high frequency I and Q signals.
14. The frequency synthesizing method of claim 9, wherein the generating the first local signal and the second local signal comprises:
generating at a first oscillator a first differential signal set using a second differential signal set input via first positive and negative input terminals of the first oscillator;
receiving at a second oscillator positive and negative signals of a third differential signal set for frequency locking via second positive and negative input terminals of the second oscillator, respectively;
receiving at the second oscillator positive and negative signals of the first differential signal set via third positive and negative input terminals of the second oscillator, respectively; and
generating at the second oscillator a second differential signal set.
15. The frequency synthesizing method of claim 14, wherein a positive signal of the second differential signal is input to the first negative input terminal of the first oscillator, and a negative signal of the second differential signal is input to the first positive input terminal of the first oscillator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of demodulating an information signal of a communication system in an electronic device, comprising the steps of:
equalizing a code division multiple access (CDMA) received signal;
despreading the CDMA received signal after said equalizing;
making a decision for information symbols after said despreading; and
using the decision for the information symbols and the CDMA received signal to perform parallel interference cancellation wherein said parallel interference cancellation includes interference cancellation, despreading and Rake receiving.
2. The method of claim 1, wherein said communication system is a multipath propagation environment where each received signal path experiences interference from other signals and other paths of the same signal.
3. The method of claim 1, wherein said despreading includes use of spreading codes.
4. The method of claim 1, wherein said despreading includes use of scrambling and spreading codes.
5. The method of claim 1 further comprising making at least one decision on a signal resulting from said parallel interference cancellation.
6. The method of Claim 5, further comprising performing another stage of interference cancellation on the signal resulting from said parallel interference cancellation after said decision.
7. The method of claim 6, further comprising making a final decision on the signal resulting from said parallel interference cancellation after said another stage of interference cancellation.
8. The method of claim 1 wherein said decision comprise clipping.
9. A method of despreading multiple codes in a communication receiver, comprising the steps of:
equalizing a code division multiple access (CDMA) received signal;
despreading the CDMA received signal after said equalizing;
deciding the value of information symbols associated with said received signal after said despreading; and
using the decided value of said information symbols and the CDMA received signal to perform parallel interference cancellation wherein said parallel interference cancellation includes interference cancellation, despreading and Rake receiving.
10. The method of claim 9 further comprising making at least one decision on a signal resulting from said parallel interference cancellation.
11. The method of Claim 10, further comprising performing another stage of interference cancellation on the signal resulting from said parallel interference cancellation after said decision.
12. The method of claim 11, further comprising making a final decision on the signal resulting from said parallel interference cancellation after said another stage of interference cancellation.
13. A receiver, comprising:
an equalizer for equalizing a code division multiple access (CDMA) received signal;
a despreader for despreading the equalized CDMA received signal; and
a parallel interface canceller having an input for receiving said equalized CDMA received signal and another input for receiving said CDMA received signal wherein said parallel interference canceller implements interference cancellation, despreading and a Rake receiver.
14. The receiver of claim 13, wherein said despreader implements spreading codes.
15. The receiver of claim 13, wherein said despreader implements scrambling and spreading codes.
16. The receiver of claim 13, further comprising decision circuitry coupling said despreader to said parallel interference canceller circuit.
17. The receiver of claim 16, further comprising a second decision circuitry coupling said parallel interference canceller circuit to another interference canceller circuit.
18. The receiver of claim 17, further comprising at least one additional decision circuitry coupling said second decision circuitry to said another interference canceller circuit.
19. The receiver of claim 18, further comprising yet another decision circuitry coupled to an output of said another interference canceller circuit.