1. A processing system, comprising:
a buffer;
a hardware processor that includes
an execution unit;
a plurality of software accessible registers; and
a data moving engine coupled to the execution unit, the software accessible registers, and the buffer,
wherein execution of a first instruction associates a memory address of the buffer with one of the software accessible registers, and thereafter the data moving engine resolves a conditional branch instruction, which specifies the one of the software accessible registers, by testing a value corresponding to a number of elements to be accessed from the buffer, wherein the value is stored in a location which is determined based on the memory address of the buffer, wherein the location is not part of the buffer.
2. The processing system of claim 1, wherein the first instruction is a read-tie instruction.
3. The processing system of claim 1, wherein the memory address of the buffer is associated with a register address of the one of the software accessible registers as a result of writing a value to a co-processor register.
4. The processing system of claim 1, wherein a memory transaction determines the number of elements to be accessed from the buffer.
5. The processing system of claim 1, wherein the data moving engine includes a binding table that maintains at least one association between the memory address of the buffer and a register address of the one of the software accessible registers.
6. The processing system of claim 1, wherein the one of the software accessible registers is one of a general purpose register, an accumulation register, a floating point unit register, and a co-processor register.
7. The processing system of claim 1, wherein the buffer is a stream buffer.
8. The processing system of claim 1, wherein the location corresponds to a counter register.
9. A hardware processor, comprising:
an execution unit;
a plurality of software accessible registers coupled to the execution unit; and
a data moving engine coupled to the execution unit and the software accessible registers;
wherein execution of a first instruction associates a memory address of a buffer coupled to the hardware processor with one of the software accessible registers, and thereafter the data moving engine resolves a conditional branch instruction, which specifies the one of the software accessible registers, by testing a value corresponding to a number of elements to be accessed from the buffer, wherein the value is stored in a location which is determined based on the memory address of the buffer, wherein the location is not part of the buffer.
10. The hardware processor of claim 9, wherein the first instruction is a read-tie instruction.
11. The hardware processor of claim 9, wherein the memory address of the buffer is associated with a register address of the one of the software accessible registers as a result of writing a value to a co-processor register.
12. The hardware processor of claim 9, wherein the data moving engine includes a binding table that maintains at least one association between the memory address of the buffer and a register address of the one of the software accessible registers.
13. The hardware processor of claim 9, wherein the one of the software accessible registers is one of a general purpose register, an accumulation register, a floating point unit register, and a co-processor register.
14. The hardware processor of claim 9, wherein the location corresponds to a counter register.
15. A computer program product comprising a non-transitory computer readable storage medium, the computer readable storage medium having embodied thereon computer readable program code for generating a processor core, the computer readable program code comprising:
first computer readable program code for generating an execution unit;
second computer readable program code for generating a plurality of software accessible registers; and
third computer readable program code for generating a data moving engine coupled to the execution unit and the software accessible registers;
wherein execution of a first instruction associates a memory address of a buffer coupled to the processor core with one of the software accessible registers, and thereafter the data moving engine resolves a conditional branch instruction, which specifies the one of the software accessible registers, by testing a value corresponding to a number of elements to be accessed from the buffer, wherein the value is stored in a location which is determined based on the memory address of the buffer, wherein the location is not part of the buffer.
16. The computer program product of claim 15, wherein the first instruction is a read-tie instruction.
17. The computer program product of claim 15, wherein the memory address of the buffer is associated with a register address of the one of the software accessible registers as a result of writing a value to a co-processor register.
18. The computer program product of claim 15, wherein the data moving engine includes a binding table that maintains at least one association between the memory address of the buffer and a register address of the one of the software accessible registers.
19. The computer program product of claim 15, wherein the one of the software accessible registers is one of a general purpose register, an accumulation register, a floating point unit register, and a co-processor register.
20. The computer program product of claim 15, wherein the processor core is embodied in hardware description language software.
21. The computer program product of claim 15, wherein the processor core is embodied in one of Verilog hardware description language software and VHDL hardware description language software.
22. The computer program product of claim 15, wherein the location corresponds to a counter register.
23. A method for resolving a conditional branch in a processing system, the processing system including a buffer and a processor that has a data moving engine, an execution unit, and a plurality of software accessible registers, the method comprising:
(1) associating a memory address of the buffer with a register address of a first software accessible register upon executing an instruction;
(2) decoding a conditional branch instruction that specifies the first software accessible register; and
(3) in response to executing the conditional branch instruction, testing a value corresponding to a number of elements to be accessed from the buffer, wherein the value is stored in a location which is determined based on the memory address of the buffer, wherein the location is not part of the buffer, to resolve the conditional branch instruction.
24. The method of claim 23, wherein step (1) comprises executing an instruction that associates the memory address of the buffer with a register address of one of a general purpose register, an accumulation register, a floating point unit register, and a co-processor register.
25. The method of claim 24, wherein step (1) comprises executing a read-tie instruction.
26. The method of claim 23, wherein the location corresponds to a counter register.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. For an instrument responsive to recipe parameters, a method for creating a recipe, the method comprising:
accessing mask set data;
recognizing a target structure in the mask set data;
extracting parameters from the mask set data; and
configuring the recipe based on the extracted parameters responsive to the recognized target structure, wherein the configuration of the recipe is performed before a wafer printed with a mask created from the mask set data is generated.
2. The method of claim 1 wherein the parameters for a process layer are queried from a database.
3. The method of claim 1 wherein the extracted parameters comprises at least one of wafer processing parameters, inspection parameters, and control parameters.
4. The method of claim 1 wherein the target structure comprises at least one of alignment site, measurement site, overlay target, and array element.
5. For an instrument instructed by a recipe to perform a task on a wafer, a method comprising:
receiving design data describing a die;
extracting parameters from the design data relevant to the configuration of the instrument; and
creating from the extracted parameters, the recipe for performing the task, wherein the recipe is created before a wafer to which the design data has been applied is generated.
6. The method of claim 5 wherein the task includes at least one of inspection and metrology.
7. The method of claim 5 further comprising applying the extracted parameters to at least one die on the wafer using a stepper setup file.
8. The method of claim 5 wherein the design data includes at least one of element names and instance types.
9. The method of claim 5 further comprising inspecting the wafer using the recipe.
10. The method of claim 9 wherein the inspecting is micro inspection.
11. The method of claim 9 wherein the inspecting is macro inspection.
12. The method of claim 9 wherein the inspecting is darkfield inspection.
13. The method of claim 5 further comprising measuring the wafer using the recipe.
14. The method of claim 13 wherein the measuring is film measurement.
15. The method of claim 13 wherein the measuring is critical dimension measurement.
16. The method of claim 13 wherein the measuring is overlay measurement.
17. A recipe extraction system using design data specifying one or more die, the system comprising:
an access module to access the design data describing a die;
an analyzer to extract parameters from the design data; and
a configuration module to produce a recipe for controlling one of an inspection and a metrology instrument, wherein the configuration module produces the recipe before a wafer to which the design data has been applied is generated.
18. The system of claim 17 wherein the access module is a network interface.
19. The system of claim 17 wherein the analyzer performs overlay recipe extraction.
20. The system of claim 17 wherein the analyzer performs inspection recipe extraction.
21. The system of claim 17 wherein the recipe is a set of instructions for measuring a wafer.
22. The system of claim 17 wherein the recipe is a set of instructions for inspecting a wafer.
23. An inspectionmetrology instrument using design data specifying one or more die, the instrument comprising:
an input interface for accessing the design data describing a die;
an analyzer to recognize target structures in the design data and extract parameters from the design data; and
a recipe module creating a recipe based on the extracted parameters responsive to the recognized target structure, wherein the recipe module creates the recipe before a wafer to which the design data has been applied is generated.