1. An industrial network system comprising:
a host computer including a display unit, an information input unit, and software;
a central communication unit including a host computer interface unit, a first IO data storing unit, a second IO data storing unit, an identification number storing unit, a communication cycle data storing unit, at least one communication port, at least two fifo type storing units per one communication port and a central communication control unit; and
a plurality of terminal communication units each including one upstream communication port, at least two downstream communication ports, at least two fifo type storing units per one downstream communication port, at least one IO port, a terminal communication control unit, an identification number storing unit, a priority order number storing unit, and a communication cycle information storing unit,
wherein:
the upstream communication ports of the terminal communication units are connected to the at least one communication port in the central communication unit or to a downstream communication port of any other terminal communication unit in the plurality of terminal communication units;
the central communication unit sends to the terminal communication units individual values of communication cycles required for every control object that is stored in the communication cycle information storing unit from the host computer;
each terminal communication unit stores the received individual value based on the communication cycle in the communication cycle information storing unit and transfers output data at a cycle based on a value sent to the respective terminal communication unit;
the central communication unit causes to store an input value of the IO port received from each terminal communication unit in a first input data storing unit, and causes to store the input value in the first input data storing unit in a second input data storing unit based on the communication cycle in the communication cycle information storing unit; and
the host computer confirms values of the IO ports of the respective terminal communication units with reference to the second input data storing unit of the central communication unit.
2. The industrial network system according to claim 1, wherein:
the central communication unit sends to the terminal communication units numbers representing priority orders of data communication from the host computer stored in the priority order number storing unit,
each terminal communication unit is capable of storing the received priority order number in the priority order number storing unit, when the central communication unit sends output data to each terminal communication unit,
the central communication unit causes to store the output data in the fifo type storing units corresponding to the priority order number of each terminal communication unit,
the at least one communication port of the central communication unit takes out orderly the output data from the fifo type storing units according to the priority order and sends the output data,
each terminal communication unit forms an input data packet by combining an input value from the IO port and priority order number information stored in the priority order number storing unit and outputs the input data packet to the upstream communication port,
data from the downstream communication port are stored in separate fifo type storing units corresponding to the priority order number of the input data packet, and
input data packets stored in the fifo type storing units are orderly sent out according to the priority order to the upstream communication port.
3. The industrial network system according to claim 1, wherein a summed value of values of communication cycles stored in the communication cycle information storing units in all of the terminal communication units connected to a network is set below the maximum performance of the network.
4. The industrial network system according to claim 3, wherein in order to maintain the communication cycles required for the respective control objects, values of priority order numbers is set so that time variability of the communication cycles of the terminal communication units is confined within a range of one cycle.
5. The industrial network system according to claim 1, wherein set values of priority order numbers of the terminal communication units and a number of terminal communication units to be passed from the central communication unit to an objective terminal communication unit are set based on a communication delay time from a control object to the host computer required for the respective control devices.
6. The industrial network system according to claim 1, wherein the software in the host computer is provided with a function capable of setting the communication cycle required for the control object from the information input unit.
7. The industrial network system according to claim 1, wherein the software in the host computer is provided with a function capable of setting the communication cycles required for all of the control objects, a maximum allowable communication delay time and a connection configuration depth of the terminal communication units on a network from the information input unit.
8. The industrial network system according to claim 7, wherein the setting function and the display function of the network constitution included in the software of the host computer are implemented through a graphical user interface (GUI).
9. The industrial network system according to claim 1, wherein a plurality of control devices constituting a chip mounter is connected to the plurality of terminal communication units.
10. An industrial network system comprising:
a host computer including a display unit, an information input unit, and software;
a central communication unit including a host computer interface unit, a first IO data storing unit, a second IO data storing unit, an identification number storing unit, a communication cycle data storing unit, at least one communication port, at least two fifo type storing units per one communication port and a central communication control unit; and
a plurality of terminal communication units each including one upstream communication port, at least two downstream communication ports, at least two fifo type storing units per one downstream communication port, at least one IO port, a terminal communication control unit, an identification number storing unit, a priority order number storing unit, and a communication cycle information storing unit,
wherein:
the upstream communication ports of the terminal communication units are connected to the at least one communication port in the central communication unit or to a downstream communication port of any other terminal communication unit in the plurality of terminal communication units;
the host computer determines communication delay times from terminal communication units for the respective control objects by making use of priority of terminal communication units, a number of communication packets of terminal communication units of which priority is equal to or higher than the priority order set for the terminal communication unit, communication time per one communication path and the number of terminal communication units to be passed from the central communication unit to an objective terminal communication unit; and
the host computer changes the priority of the respective terminal communication units so as to fulfill a communication delay time required for the control object and sets the priority of the terminal communication unit.
11. An industrial network system comprising:
a host computer including a display unit, an information input unit, and software;
a central communication unit including a host computer interface unit, a first IO data storing unit, a second IO data storing unit, an identification number storing unit, a communication cycle data storing unit, at least one communication port, at least two fifo type storing units per one communication port and a central communication control unit; and
a plurality of terminal communication units each including one upstream communication port, at least two downstream communication ports, at least two fifo type storing units per one downstream communication port, at least one IO port, a terminal communication control unit, an identification number storing unit, a priority order number storing unit, and a communication cycle information storing unit,
wherein:
the upstream communication ports of the terminal communication units are connected to the at least one communication port in the central communication unit or to a downstream communication port of any other terminal communication unit in the plurality of terminal communication units;
the host computer determines communication delay times from terminal communication units for the respective control objects by making use of priority of terminal communication units, a number of communication packets of terminal communication units of which priority is equal to or higher than the priority order set for the terminal communication unit, communication time per one communication path and the number of terminal communication units to be passed from the central communication unit to an objective terminal communication unit; and
the host computer changes the layout of the control object so as to fulfill a communication delay time required for the control object and sets the number of terminal communication units to be passed from the central communication unit to an objective terminal communication unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A focal plane array, comprising:
an imaging array section, comprising:
an array of electromagnetic radiation detectors; and
an address decoder for providing outputs from selectively enabled detectors; and
wherein the imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit;
test circuitry, for providing test signals to sequentially test each one of the primary circuits and determining whether a response from the test signal provided to the tested primary circuit is proper or improper and for storing in the test circuitry in response to such determining a select signal associated with each one of the tested circuit blocks;
an array controller for, during a subsequent normal operating mode, provides timing pulses to the address decoder for selectively enabling the detectors using either the primary or redundant circuits in each one of the plurality of circuit blocks selectively in accordance with the stored select signal associated with such one of the circuit blocks.
2. The focal plane array recited in claim 1 wherein one of the circuit blocks is a Timing Signal circuit block.
3. The focal plane array recited in claim 1 wherein one of the circuit blocks is an Address Decoder Section Block.
4. The focal plane array recited in claim 1 wherein one of the circuit blocks is Row Address Enable Block.
5. The focal plane array recited in claim 1 wherein one of the circuit Mocks is an Imaging Array Column Output Section.
6. The focal plane array recited in claim 1 wherein one of the circuit blocks is an Imaging Array Column Output Section includes a plurality of column output sections.
7. A focal plane array, comprising:
a first semiconductor wafer having formed therein an array of electromagnetic radiation detectors;
a semiconductor structure, connected to the array of detectors, having:
an imaging array section comprises a plurality of circuit blocks, each one of the circuit blocks having a primary circuit and a redundant circuit; and
a processor, the processor comprising:
a test module; and
a storage element; and
wherein:
during a test mode, the test module operates to test the primary circuit of each one of the plurality of circuit blocks and determine whether a response is proper or improper from the test and for storing in the storage element in response to such determining a select signal associated with each one of the tested circuit blocks; and
during a subsequent normal operating mode, the processor provides timing pulses to the imaging array section for selectively responding to radiation sensed by the detectors using either the primary or redundant circuit in each one of the plurality of circuit blocks selectively in accordance with the stored select signal associated with such one of the circuit blocks.
8. A semiconductor structure, comprising:
a first semiconductor having formed thereon an array of electromagnetic radiation detectors;
a semiconductor structure electrically connected to the first semiconductor substrate, the second semiconductor substrate having formed thereon:
primary and redundant circuits each comprising a plurality of circuit blocks arranged for controlling readout of packets of charge stored wells of the detectors and for converting the readout stored packets into corresponding voltages and for converting such voltages into corresponding digital signals; and
a test section for, upon detection of a fault in the primary circuit section, or in one of the primary circuit blocks, decoupling the primary circuit, or fault detected, circuit block, from the array and replacing the primary circuit, or the fault detected circuit block, with the redundant circuit, or with a corresponding one of the circuit blocks, in the redundant circuit.
9. The focal plane array recited in claim 1 wherein the test section tests for proper logic operation of the circuit blocks of the primary section,
10. The focal plane array recited in claim 1 wherein the test section tests for signal integrity in the circuit blocks of the primary section.
11. The focal plane array recited in claim 1 wherein the test section tests for signal integrity in the row and column addressing blocks of the primary section.
12. The focal plane array recited in claim 1 wherein the test section tests for signal integrity in circuitry for converting the voltages into corresponding digital signals;