1460915913-477c2577-e710-4a7c-9417-ac5f6dff2917

1. A continuous process for producing a chlorohydrin selected from the group consisting of chloropropanediol, dichloropropanol and a mixture thereof, wherein glycerol, an ester of glycerol or a mixture thereof is reacted with a chlorinating agent and an organic acid in a liquid reaction medium whose steady-state composition comprises glycerol and esters of glycerol whose sum content, expressed as moles of glycerol, is greater than 2.0 mol % and less than or equal to 30 mol %, the percentage being based on the organic part of the liquid reaction medium.
2. The process according to claim 1, wherein the composition of the liquid reaction medium in the steady state comprises the chlorohydrin and chlorohydrin esters whose sum content, expressed as moles of chlorohydrin, is greater than or equal to 10 mol % and less than or equal to 98 mol %, the percentage being based on the organic part of the liquid reaction medium.
3. The process according to claim 1, wherein the composition of the liquid reaction medium in the steady state further comprises chlorinated oligomers of glycerol and esters of chlorinated oligomers of glycerol whose sum content, expressed as moles of glycerol, is greater than or equal to 0.1 mol % and less than or equal to 20 mol %, the percentage being based on the organic part of the liquid reaction medium.
4. The process according to claim 1, wherein the chlorohydrin is a mixture of chloropropanediol and dichloropropanol.
5. The process according to claim 4, wherein the composition of the liquid reaction medium in the steady state comprises the chloropropanediol and chloropropanediol esters whose sum content, expressed as moles of chloropropanediol, is greater than or equal to 11 mol % and less than or equal to 85 mol %, the percentage being based on the organic part of the liquid reaction medium.
6. The process according to claim 4, wherein the composition of the liquid reaction medium in the steady state comprises the dichloropropanol and dichloropropanol esters whose sum content, expressed as moles of dichloropropanol, is greater than or equal to 0.5 mol % and less than or equal to 79 mol %, the percentage being based on the organic part of the liquid reaction medium.
7. The process according to claim 1, wherein the glycerol, the ester of glycerol or the mixture thereof is obtained starting from renewable raw materials.
8. The process according to claim 1, wherein the chlorinating agent is gaseous hydrogen chloride.
9. The process according to claim 1, wherein the organic acid is an impurity present in the glycerol, the ester of glycerol or the mixture thereof.
10. The process according to claim 1, wherein the organic acid is used as a catalyst of the chlorination reaction.
11. The process according to claim 3, wherein the esters of glycerol, of the chlorohydrin and of the chlorinated oligomers of glycerol result from reactions of the organic acid with glycerol, the chlorohydrin and the chlorinated oligomers of glycerol.
12. The process according to claim 1, wherein said process produces at least some dichloropropanol, and further comprising preparation of epichlorohydrin by dehydrochlorination of dichloropropanol.
13. The process according to claim 12, further comprising using the epichlorohydrin in the production of an epoxy resin.
14. The process according to claim 1, wherein the organic acid is a carboxylic acid having an atmospheric boiling point of greater than or equal to 200\xb0 C.
15. The process according to claim 14, wherein the organic acid is adipic acid.
16. The process according to claim 1, wherein said glycerol, an ester of glycerol or a mixture thereof is reacted with a chlorinating agent and an organic acid at a temperature of at least 20\xb0 C. and not more than 160\xb0 C. in a liquid reaction medium.
17. The process according to claim 14, wherein said glycerol, an ester of glycerol or a mixture thereof is reacted with a chlorinating agent and an organic acid at a temperature of at least 20\xb0 C. and not more than 160\xb0 C., a pressure of at least 0.3 bar and not more than 100 bar, and for a residence time of at least 1 h and not more than 50 h, in a liquid reaction medium.
18. The process according to claim 15, wherein said glycerol, an ester of glycerol or a mixture thereof is reacted with a chlorinating agent and an organic acid at a temperature of at least 20\xb0 C. and not more than 160\xb0 C., a pressure of at least 0.3 bar and not more than 100 bar, and for a residence time of at least 1 h and not more than 50 h, in a liquid reaction medium.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A precharge circuit comprising:
a precharge control unit configured to generate a read precharge signal and a write precharge signal in response to a read signal, a write signal, and a precharge signal;
a first precharge unit configured to precharge a data inputoutput line to a first voltage level in response to the read precharge signal; and
a second precharge unit configured to precharge the data inputoutput line to either a second voltage level or a third voltage level in response to the write precharge signal,
wherein the second voltage level is lower than the third voltage level, and the third voltage level is lower than the first voltage level,
wherein the second voltage level corresponds to a half of the first voltage level.
2. The precharge circuit of claim 1, wherein the precharge control unit enables the read precharge signal when the read signal and the precharge signal are enabled, and enables the write precharge signal when the write signal and the precharge signal are enabled.
3. The precharge circuit of claim 1, wherein the precharge control unit enables the read precharge signal when the precharge signal is enabled, and disables the read precharge signal and the write precharge signal when the precharge signal is disabled.
4. A precharge circuit comprising:
a precharge control unit configured to generate a read precharge signal and a write precharge signal in response to a write signal, a write end signal, and a precharge signal;
a first precharge unit configured to precharge a data inputoutput line to a first voltage level in response to the read precharge signal; and
a second precharge unit configured to precharge the data inputoutput line to either a second voltage level or a third voltage level in response to the write precharge signal,
wherein the second voltage level is lower than the third voltage level, and the third voltage level is lower than the first voltage level,
wherein the second voltage level corresponds to a half of the first voltage level.
5. The precharge circuit of claim 4, wherein the precharge control unit enables the read precharge signal when the write end signal and the precharge signal are enabled, and enables the write precharge signal when the write signal and the precharge signal are enabled.
6. The precharge circuit of claim 4, wherein the precharge control unit enables the read precharge signal when the precharge signal is enabled, and disables the read precharge signal and the write precharge signal when the precharge signal is disabled.
7. A semiconductor memory apparatus comprising:
a first data inputoutput line configured to transfer data; and
a precharge circuit configured to precharge the first data inputoutput line to a first voltage level during a read operation, and to precharge the first data inputoutput line to either a second voltage level or a third voltage level during a write operation,
wherein the second voltage level is lower than the third voltage level, and the third voltage level is lower than the first voltage level,
wherein the second voltage level corresponds to a half of the first voltage level.
8. The semiconductor memory apparatus of claim 7, wherein the precharge circuit comprises:
a precharge control unit configured to generate a read precharge signal and a write precharge signal in response to a write signal and a precharge signal;
a first precharge unit configured to precharge the first data inputoutput line to the first voltage level in response to the read precharge signal; and
a second precharge unit configured to precharge the first data inputoutput line to either the second voltage level or the third voltage level in response to the write precharge signal.
9. The semiconductor memory apparatus of claim 8, wherein the precharge control unit generates the read precharge signal and the write precharge signal in response to the write signal, the precharge signal, and a read signal.
10. The semiconductor memory apparatus of claim 8, wherein the precharge control unit generates the read precharge signal and the write precharge signal in response to the write signal, the precharge signal, and a write end signal.
11. The semiconductor memory apparatus of claim 9, wherein the precharge control unit enables the read precharge signal when the read signal and the precharge signal are enabled, and enables the write precharge signal when the write signal and the precharge signal are enabled.
12. The semiconductor memory apparatus of claim 9, wherein the precharge control unit enables the read precharge signal when the precharge signal is enabled, and disables the read precharge signal and the write precharge signal when the precharge signal is disabled.
13. The semiconductor memory apparatus of claim 7, further comprising a voltage supplying unit configured to provide one of the second and third voltages to the precharge circuit in response to a voltage selection signal.
14. The semiconductor memory apparatus of claim 7, wherein the first data inputoutput line is coupled to a second data inputoutput line through an inputoutput switch, which is configured to receive an inputoutput switch signal, and the second data inputoutput line is coupled to a bit line and a memory cell through a column switch, which configured to receive a column selection signal.
15. The semiconductor memory apparatus of claim 7, wherein the first data inputoutput line is coupled to a third data inputoutput line through an inputoutput driving unit.
16. The semiconductor memory apparatus of claim 15, wherein the inputoutput driving unit drives the first data inputoutput line according to a voltage level of a data, which is transmitted through the third data inputoutput line, during the write operation, and outputs data, which is generated by sensing variation of a voltage level of the first data inputoutput line, to the third data inputoutput line during the read operation.