1. An address translation logic that generates an instruction’s operand address, said address translation logic comprising:
an address generation circuit having at least one adder that performs partial sum addition of said instruction operand’s base register value with a displacement value in said instruction; and
a carry prediction history block that provides a predicted carry-in value to said at least one adder during said partial sum addition, wherein said carry prediction history block is associated with said instruction, and wherein said carry prediction history block includes a predicted row access select (RAS) carry-in value and a predicted column access select (CAS) carry-in value.
2. The address translation logic as recited in claim 1, wherein said carry prediction history block further includes a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for said instruction were correct.
3. The address translation logic as recited in claim 1, wherein said carry prediction history block is appended to said instruction.
4. The address translation logic as recited in claim 2, wherein said at least one adder includes a ten bit adder that generates an actual row access select (RAS) carry-in value and a three bit adder that generates an actual column access select (CAS) carry-in value.
5. The address translation logic as recited in claim 4, wherein said address generation circuit further includes first and second comparators that compare said actual RAS carry-in value with said predicted RAS carry-in value and said actual CAS carry-in value with said predicted CAS carry-in value, respectively.
6. The address translation logic as recited in claim 5, wherein said address generation circuit further includes a logical OR block coupled to said first and second comparators that determines whether to replace said predicted RAS and CAS carry-in values with said actual RAS and CAS carry-in values in said carry prediction history block.
7. The address translation logic an recited in claim 5, wherein said address generation circuit further comprises:
a RAS carry-in selector and a CAS carry-in selector; and
a displacement size detection logic, coupled to said RAS and CAS carry-in selectors, that selectively controls the operation of said RAS and CAS carry-in selectors in response to a determination of a size of said displacement value.
8. The address translation logic as recited in claim 7, wherein said RAS and CAS carry-in selector selects a value of zero responsive to said displacement size detection logic determining that said size of displacement value is positive and less than five significant bits.
9. The address translation logic as recited in claim 6, wherein said actual RAS and CAS carry-in values replace said predicted RAS and CAS carry-in values in said carry prediction history block responsive to either of said predicted RAS carry-in value not being equal to said actual RAS carry-in value and said predicted CAS carry-in value not being equal to said actual CAS carry-in value.
10. A method for efficiently generating an instruction’s operand address, comprising:
associating a carry prediction history block with said instruction, wherein said carry prediction history block contains at least one predicted carry-in value corresponding to said instruction;
providing said at least one predicted carry-in value to a address generation circuit having at least one adder that performs a partial sum addition of said instruction operand’s base register value with a displacement value in said instruction, wherein said at least one predicted carry-in value includes a predicted row access select (RAS) carry-in value and a predicted column access select (CAS) carry-in value of said instruction; and
utilizing said predicted carry-in value in said partial sum addition.
11. The method as recited in claim 10, wherein said carry prediction history block further includes a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for said instruction were correct.
12. The method as recited in claim 10, further comprising appending said carry prediction history block to said instruction.
13. The method as recited in claim 11, further comprising generating an actual row access select (RAS) carry-in value and an actual column access select (CAS) carry-in value.
14. The method as recited in claim 13, further comprising:
comparing said actual RAS carry-in value with said predicted RAS carry-in value and said actual CAS carry-in value with said predicted CAS carry-in value, respectively; and
replacing said predicted RAS and CAS carry-in values in said carry prediction history block responsive to either of said predicted RAS carry-in value not being equal to said actual RAS carry-in value and said predicted CAS carry-in value not being equal to said actual CAS carry-in value.
15. The method as recited in claim 14, further comprising:
determining a size of said displacement value;
selecting a value of zero for said RAS and CAS carry-in values responsive to a determination that said size of displacement value is positive and less than five significant bits.
16. A computer-readable medium having stored thereon a data structure for an instruction, said data structure comprising:
a first field containing data representing an operation code;
a second field containing data representing a register address;
a third field containing data representing a displacement; and
a fourth field containing data representing predicted carry-in values for partial sum addition in determining said instruction’s operand address, wherein said predicted carry-in values include a predicted row access select (RAS) carry-in value and a predicted column access select (CAS) carry-in value.
17. The computer-readable medium as recited in claim 16, wherein said predicted carry-in values further comprise a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for said instruction were correct.
18. A data processing system, comprising:
a memory system;
a processor, coupled to said memory system, wherein said processor including a load store unit having an address translation logic for generating an instruction’s operand address, said address translation logic comprising:
an address generation circuit having at least one adder that performs partial sum addition of said instruction operand’s base register value with a displacement value in said instruction; and
a carry prediction history block that provides a predicted carry-in value to said at least one adder during said partial sum addition, wherein said carry prediction history block is associated with said instruction, and wherein said carry prediction history block includes a predicted row access select (RAS) carry-in valve, a predicted column access select (CAS) carry-in value, and a confirmation flag that indicates whether the previous carry-in predictions for the previous predicted RAS and CAS carry-in values for said instruction were correct.
19. The data processing system as recited in claim 18, wherein said at least one adder includes a ten bit adder that generates an actual row access select (RAS) carry-in value and a three bit adder that generates an actual column access select (CAS) carry-in value.
20. The data processing system as recited in claim 19, wherein said address generation circuit further includes first and second comparators that compare said actual RAS carry-in value with said predicted RAS carry-in value and said actual CAS carry-in value with said predicted CAS carry-in value, respectively.
21. The data processing system as recited in claim 19, wherein said address generation circuit further includes a logical OR block coupled to said first and second comparators that determines whether to replace said predicted RAS and CAS carry-in values with said actual RAS and CAS carry-in values in said carry prediction history block.
22. The data processing system as recited in claim 21, wherein said address generation circuit further comprises:
a RAS carry-in selector and a CAS carry-in selector; and
a displacement size detection logic, coupled to said RAS and CAS carry-in selectors, that selectively controls the operation of said RAS and CAS carry-in selectors in response to a determination of a size of said displacement value.
23. The data processing system as recited in claim 22, wherein said RAS and CAS carry-in selectors selects a value of zero responsive to said displacement size detection logic determining that said size of displacement value is positive and less than five significant bits.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A disk carrying device comprising:
a transporting roller for carrying a disk to a chucking position;
a turntable and a damper for holding the disk carried to the chucking position;
a cam plate for moving at least the turntable or the damper;
a trigger plate, which is moved by carrying of the disk to the chucking position, for changing a transmission route of driving force from the transporting roller to the cam plate;
a first biasing means for urging the trigger plate to a position before moving;
a guide base for pressing the disk on the transporting roller;
an arm roller which is disposed on an opposite side of the guide base with respect to the transporting roller so as to move the guide base apart from the transporting roller;
a second biasing means disposed between the guide base and the arm roller; and
a shutter provided on the arm roller for closing a disk slot in cooperation with an operation of the guide base being separated from the transporting roller;
wherein the guide base and the arm roller abut with each other when the disk is not present between the guide base and the arm roller;
the second biasing means is attached to the guide base and the arm roller such that abutting parts of the guide base and the arm roller are held in an abutted state by urging force of the second biasing means;
the second biasing means is extended when the disk is present between the guide base and the transporting roller and generates urging force pulling the guide base to the transporting roller;
the cam plate is provided with a cam hole for moving the arm roller, and the arm roller is moved by a movement of the trigger plate through the cam hole of the cam plate at a time of playing of the disk, and the guide base and the transporting roller are moved to be apart from each other against the second biasing means to be located out of a disk playing space; and
movement of at least the turntable or the damper, and movement of the arm roller are operated by the cam plate.
2. The disk carrying device according to claim 1, wherein the second biasing means is disposed near an abutting position of the guide base with the arm roller.
3. The disk carrying device according to claim 1, wherein the first biasing means and the second biasing means are each a coil spring.
4. The disk carrying device according to claim 3, further comprising:
a motor included in the transmission route of driving force;
an intermediate gear which is included in the transmission route of driving force and which is rotationally driven by the motor and is axially movable; and
an arm cam which is provided between the trigger plate and the cam plate so as to be swung by the trigger plate for transmitting movement of the trigger plate to the cam plate,
wherein the intermediate gear is axially moved by the arm cam to change the driving force of the motor from the transporting roller to the cam plate.