1. A distorted aberration correction processing apparatus, comprising:
a first memory area;
a second memory area;
a first address control circuit for reading out an image signal in the first memory area on a unit basis of an area including a plurality of the image signals, along a curve corresponding to a distorted aberration of an optical system, and writing the image signal read out on the area basis in the second memory area; and
a second address control circuit for reading out an image signal in the second memory area on an image signal basis, and outputting the image signal read out on the image signal basis to an output portion so as to suppress the distorted aberration of the optical system, wherein the first address control circuit effects control so that the image signal for each of the areas is sequentially read out in a predetermined order, and
the second address control circuit effects random access control.
2. The distorted aberration correction processing apparatus according to claim 1, wherein a width of an area comprising the plurality of image signals is an integer multiple of a burst length of the first memory area.
3. The distorted aberration correction processing apparatus according to claim 1, wherein the apparatus includes a plurality of the second memory areas and effects correction of the distorted aberration by switching between the plurality of the second memory areas.
4. The distorted aberration correction processing apparatus according to claim 1, wherein
the first address control circuit reads out the image signal in the first memory area on the unit basis of the area including a plurality of the image signals along a curve corresponding to a distorted aberration of the optical system at a zoom position of a zoom lens, and
the second address control circuit reads out the image signal in the second memory area to be written in the second memory area, on the image signal basis, and outputs the image signal read out on the image signal basis to the output portion so as to suppress the distorted aberration of the optical system at the zoom position of the zoom lens.
5. An image capture apparatus, comprising:
an optical system;
a photoelectric conversion device for picking up an object image;
a first memory area for storing an image signal from the photoelectric conversion device;
a second memory area;
a first address control circuit for reading out an image signal in the first memory area on a unit basis of an area including a plurality of the image signals along a curve corresponding to a distorted aberration of the optical system, and writing the image signal read out on the area basis in the second memory area; and
a second address control circuit for reading out an image signal in the second memory area on the pixel signal basis, and outputting the image signal read out on the pixel signal basis to an output portion so as to suppress the distorted aberration of the optical system, wherein the first address control circuit effects control so that the signal read out on the area basis is sequentially read out in a predetermined order, and
the second address control circuit effects random access control.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A liquid crystal display (LCD) device connectable to a power source, comprising:
a substrate;
a panel including an array of thin film transistors provided on the substrate; and
a first integrated circuit (IC), including
a timing controller for providing control signals and video signals,
a source driver for receiving the control signals and video signals and driving the panel, and
a common voltage circuit for providing a common voltage to the panel.
2. The LCD device of claim 1, wherein the substrate comprises glass.
3. The LCD device of claim 1, wherein the panel includes a plurality of pixel elements arranged to form a triangular array known as a delta configuration.
4. The LCD device of claim 1, wherein the thin film transistors of the panel are formed using an amorphous silicon technique.
5. The LCD device of claim 1, wherein the thin film transistors of the panel are formed using a low temperature polysilicon technique.
6. The LCD device of claim 1, wherein the integrated circuit is mounted on the substrate using a chip-on-glass (COG) technique.
7. The LCD device of claim 1, wherein the first IC is connectable to a reference voltage and an amplitude of the common voltage is adjusted in accordance with the reference voltage.
8. The LCD device of claim 1, wherein the first IC further comprises a common voltage adjustment circuit for adjusting an amplitude of the common voltage.
9. The LCD device of claim 1, the first IC being connectable to a microprocessor, wherein the microprocessor is used to control the first IC.
10. The LCD device of claim 1, further comprising a gate driver provided on the substrate for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller.
11. The LCD device of claim 10, wherein the gate driver comprises thin film transistors.
12. The LCD device of claim 11, wherein the thin film transistors of the gate driver are formed on the substrate at the same time the thin film transistors of the panel are formed.
13. The LCD device of claim 1, wherein the first IC further comprises a gate driver for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller.
14. The LCD device of claim 1, further comprising a second IC including a gate driver for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller.
15. The LCD device of claim 14, wherein the second IC is mounted on the substrate using a chip-on-glass technique.
16. The LCD device of claim 1, wherein the timing controller is connectable to the power source.
17. The LCD device of claim 1, wherein the first IC further comprises a DCDC control circuit connectable to the power source and a peripheral circuit for providing one or more power supplies to the LCD device.
18. The LCD device of claim 17, wherein the peripheral circuit comprises a common voltage adjustment circuit for providing a reference voltage to the common voltage circuit for adjusting an amplitude of the common voltage.
19. The LCD device of claim 17, further comprising a gate driver, wherein the DCDC control circuit is connectable to the peripheral circuit for providing a power supply to the gate driver.
20. The LCD device of claim 17, further comprising a light source for illuminating the panel, wherein the DCDC control circuit is connectable to the peripheral circuit for providing a power supply voltage to the light source.
21. The LCD device of claim 17, wherein the peripheral circuit is provided on a printed circuit board.
22. A liquid crystal display (LCD) device connectable to a power source, comprising:
a substrate;
a panel including an array of thin film transistors provided on the substrate; and
a first integrated circuit (IC) mounted on the substrate using a chip-on-glass (COG) technique, including
a timing controller connectable to the power source for providing control signals and video signals,
a source driver for receiving the control signals and video signals and driving the panel,
a common voltage circuit for providing a common voltage to the panel, and
a first DCDC control circuit connectable to the power source for providing one or more power supplies to the LCD device.
23. The LCD device of claim 22, wherein the substrate comprises glass.
24. The LCD device of claim 22, wherein the panel includes a plurality of pixel elements arranged to form a triangular array known as a delta configuration.
25. The LCD device of claim 22, wherein the thin film transistors of the panel are formed using an amorphous silicon technique or a low temperature polysilicon technique.
26. The LCD device of claim 22, wherein the first IC is connectable to a reference voltage and an amplitude of the common voltage is adjusted by the reference voltage.
27. The LCD device of claim 22, wherein the first IC further comprises a common voltage adjustment circuit for adjusting an amplitude of the common voltage.
28. The LCD device of claim 22, the first IC being connectable to a microprocessor, wherein the microprocessor is used to control the first IC.
29. The LCD device of claim 22, further comprising a gate driver provided on the substrate for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller.
30. The LCD device of claim 29, wherein the gate driver comprises thin film transistors.
31. The LCD device of claim 30, wherein the thin film transistors of the gate driver are formed on the substrate at the same time the thin film transistors of the panel are formed.
32. The LCD device of claim 22, wherein the first IC further comprises a gate driver for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller.
33. The LCD device of claim 22, further comprising a second IC including a gate driver for driving the panel, wherein the gate driver is coupled to receive the control signals and video signals from the timing controller, and wherein the second IC is mounted on the substrate using a chip-on-glass technique.
34. The LCD device of claim 22, wherein the timing controller is connectable to the power source.
35. The LCD device of claim 22, further comprising a gate driver, wherein the first DCDC control circuit comprises a charge pump connectable to capacitors for providing a power supply to the gate driver and the common voltage circuit.
36. The LCD device of claim 22, wherein the first DCDC control circuit comprises is connectable to capacitors for providing a power supply to the source driver.
37. The LCD device of claim 22, wherein the first DCDC control circuit is connectable to a peripheral circuit, wherein the peripheral circuit is provided on the substrate.
38. The LCD device of claim 22, wherein the first DCDC control circuit is connectable to a peripheral circuit, wherein the peripheral circuit is provided on a printed circuit board.
39. The LCD device of claim 22, further including a light source for illuminating the panel, wherein the first IC further comprises a second DCDC control circuit connectable to both the power source and a peripheral circuit for generating a power supply for the light source.