What is claimed is:
1. A heat exchanger comprising: a body having a conducting portion in contact with a heat source configured along a plane, wherein the conducting portion conducts heat from the heat source to a heat exchanging layer configured within the body, the body including at least one inlet port and at least one outlet port, wherein the at least one inlet port channels fluid through the heat exchanging layer from a first side proximal to the conducting portion to a second side distal to the conducting portion.
2. The heat exchanger according to claim 1 wherein the body further comprises:
a. a first layer having the conducting portion and configured to pass fluid therealong from the at least one inlet port; and
b. a second layer coupled to the first layer, wherein the heat exchanging layer is configured between the first layer and the second layer.
3. The heat exchanger according to claim 2 wherein the first layer further comprises a recess area having a heat conducting region in contact with the heat exchanging layer.
4. The heat exchanger according to claim 2 wherein the first layer includes the at least one inlet port.
5. The heat exchanger according to claim 2 wherein the first layer includes the at least one outlet port.
6. The heat exchanger according to claim 2 wherein the second layer includes the at least one inlet port.
7. The heat exchanger according to claim 2 wherein the second layer includes the at least one outlet port.
8. The heat exchanger according to claim 1 wherein the at least one inlet port is positioned substantially parallel with respect to the plane.
9. The heat exchanger according to claim 1 wherein the at least one inlet port is positioned substantially perpendicular with respect to the plane.
10. The heat exchanger according to claim 1 wherein the at least one outlet port is positioned substantially parallel with respect to the plane.
11. The heat exchanger according to claim 1 wherein the at least one outlet port is positioned substantially perpendicular with respect to the plane.
12. The heat exchanger according to claim 8 wherein the recess area includes a plurality of fluid inlet grooves through in the heat conducting area, the fluid inlet grooves for channeling fluid from the at least one inlet port to the heat exchanging layer.
13. The heat exchanger according to. claim 8 wherein the second layer further comprises a plurality of fluid outlet grooves for channeling fluid from the heat exchanging layer to the second port.
14. The heat exchanger according to claim 1 wherein the fluid is in single phase flow conditions.
15. The heat exchanger according to claim 1 wherein at least a portion of the fluid is in two phase flow conditions.
16. The heat exchanger according to claim 1 wherein the conducting portion has a thickness dimension within the range of and including 0.3 to 0.7 millimeters.
17. The heat exchanger according to claim 1 wherein an overhang dimension is within the range of and including 0 to 15 millimeters.
18. The heat exchanger according to claim 1 wherein at least a portion of the fluid undergoes a transition between single and two phase flow conditions in the heat exchanger.
19. The heat exchanger according to claim 2 wherein the first layer is made of a material having a thermal conductivity of at least 100 WmK.
20. The heat exchanger according to claim 2 wherein the first layer further comprises a plurality of pillars configured in a predetermined pattern along the interface layer.
21. The heat exchanger according to claim 20 wherein at least one of the plurality of pillars has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
22. The heat exchanger according to claim 20 wherein at least one of the plurality of pillars has a height dimension within the range of and including 50 microns and 2 millimeters.
23. The heat exchanger according to claim 20 wherein at least two of the plurality of pillars are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
24. The heat exchanger according to claim 20 wherein at least one of the plurality of pillars includes at least varying dimension along a predetermined direction.
25. The heat exchanger according to claim 20 wherein an appropriate number of pillars are disposed in a predetermined area along the interface layer.
26. The heat exchanger according to claim 1 wherein at least a portion of the first layer has a roughened surface.
27. The heat exchanger according to claim 20 wherein the plurality of pillars include a coating thereupon, wherein the coating has an appropriate thermal conductivity of at least 10 Wm-K.
28. The heat exchanger according to claim 1 wherein the heat exchanging layer is made of a porous microstructure.
29. The heat exchanger according to claim 28 wherein the porous microstructure has a porosity within the range of and including 50 to 80 percent.
30. The heat exchanger according to claim 28 wherein the porous microstructure has an average pore size within the range of and including 10 to 200 microns.
31. The heat exchanger according to claim 28 wherein the porous microstructure has a height dimension within the range of and including 0.25 to 2.00 millimeters.
32. The heat exchanger according to claim 28 wherein the porous microstructure includes at least one pore having a varying dimension along a predetermined direction.
33. The heat exchanger according to claim 1 further comprising a plurality of microchannels disposed in a predetermined configuration along the first layer.
34. The heat exchanger according to claim 33 wherein at least one of the plurality of microchannels has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
35. The heat exchanger according to claim 33 wherein at least one of the plurality of microchannels has a height dimension within the range of and including 50 microns and 2 millimeters.
36. The heat exchanger according to claim 33 wherein at least two of the plurality of microchannels are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
37. The heat exchanger according to claim 33 wherein at least one of the plurality of microchannels has a width dimension within the range of and including 10 to 100 microns.
38. The heat exchanger according to claim 1 wherein the first layer is coupled to the heat source.
39. The heat exchanger according to claim 1 wherein the first layer is integrally formed to the heat source.
40. The heat exchanger according to claim 1 wherein the heat source is an integrated circuit.
41. The heat exchanger according to claim 1 further comprising a thermoelectric device positioned between the conducting portion and the heat source, wherein the thermoelectric device is electrically coupled to a power source.
42. The heat exchanger according to claim 41 wherein the thermoelectric device is integrally formed within the heat exchanger.
43. The heat exchanger according to claim 41 wherein the thermoelectric device is integrally formed within the heat source.
44. The heat exchanger according to claim 41 wherein the thermoelectric device is coupled to the heat exchanger and the heat source.
45. A heat exchanger configured to cool a heat source configured along a plane comprising:
a. an interface layer for performing thermal exchange with the heat source and configured to pass fluid from a first side to a second side; and
b. a manifold layer comprising:
i. a first layer in contact with the heat source and having an appropriate thermal conductivity to pass heat to the first side of the interface layer; and
ii. a second layer coupled to the first layer and in contact with the second side of the interface layer.
46. The heat exchanger according to claim 45 wherein the first layer further comprises a recess area having a heat conducting region in contact with the interface layer.
47. The heat exchanger according to claim 45 wherein the first layer includes the at least one inlet port.
48. The heat exchanger according to claim 45 wherein the first layer includes the at least one outlet port.
49. The heat exchanger according to claim 45 wherein the second layer includes the at least one inlet port.
50. The heat exchanger according to claim 45 wherein the second layer includes the at least one outlet port.
51. The heat exchanger according to claim 45 wherein the at least one inlet port is positioned substantially parallel with respect to the plane.
52. The heat exchanger according to claim 45 wherein the at least one inlet port is positioned substantially perpendicular with respect to the plane.
53. The heat exchanger according to claim 45 wherein the at least one outlet port is positioned substantially parallel with respect to the plane.
54. The heat exchanger according to claim 45 wherein the at least one outlet port is positioned substantially perpendicular with respect to the plane.
55. The heat exchanger according to claim 46 wherein the recess area includes a plurality of fluid inlet grooves through in the heat conducting region, the fluid inlet grooves for channeling fluid from at least one inlet port to the interface layer.
56. The heat exchanger according to claim 45 wherein the second layer further comprises a plurality of fluid outlet grooves for channeling fluid from the interface layer to at least one outlet port.
57. The heat exchanger according to claim 45 wherein the fluid is in single phase flow conditions.
58. The heat exchanger according to claim 45 wherein at least a portion of the fluid is in two phase flow conditions.
59. The heat exchanger according to claim 45 wherein the first layer has a thickness dimension within the range of and including 0.3 to 0.7 millimeters.
60. The heat exchanger according to claim 45 wherein an overhang dimension is within the range of and including 0 to 15 millimeters.
61. The heat exchanger according to claim 45 wherein at least a portion of the fluid undergoes a transition between single and two phase flow conditions in the heat exchanger.
62. The heat exchanger according to claim 45 wherein the thermal conductivity is at least 100 Wm-K.
63. The heat exchanger according to claim 45 wherein the first layer further comprises a plurality of pillars configured in a predetermined pattern along the first layer.
64. The heat exchanger according to claim 63 wherein at least one of the plurality of pillars has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
65. The heat exchanger according to claim 63 wherein at least one of the plurality of pillars has a height dimension within the range of and including 50 microns and 2 millimeters.
66. The heat exchanger according to claim 63 wherein at least two of the plurality of pillars are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
67. The heat exchanger according to claim 63 wherein at least one of the plurality of pillars includes at least varying dimension along a predetermined direction.
68. The heat exchanger according to claim 63 wherein an appropriate number of pillars are disposed in a predetermined area along the interface layer.
69. The heat exchanger according to claim 45 wherein at least a portion of the first layer has a roughened surface.
70. The heat exchanger according to claim 63 wherein the plurality of pillars include a coating thereupon, wherein the coating has an appropriate thermal conductivity of at least 10 Wm-K.
71. The heat exchanger according to claim 45 wherein the interface layer is made of a porous microstructure.
72. The heat exchanger according to claim 71 wherein the porous microstructure has a porosity within the range of and including 50 to 80 percent.
73. The heat exchanger according to claim 71 wherein the porous microstructure has an average pore size within the range of and including 10 to 200 microns.
74. The heat exchanger according to claim 71 wherein the porous microstructure has a height dimension within the range of and including 0.25 to 2.00 millimeters.
75. The heat exchanger according to claim 71 wherein the porous microstructure includes at least one pore having a varying dimension along a predetermined direction.
76. The heat exchanger according to claim 45 further comprising a plurality of microchannels disposed in a predetermined configuration along the first layer.
77. The heat exchanger according to claim 76 wherein at least one of the plurality of microchannels has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
78. The heat exchanger according to claim 76 wherein at least one of the plurality of microchannels has a height dimension within the range of and including 50 microns and 2 millimeters.
79. The heat exchanger according to claim 76 wherein at least two of the plurality of microchannels are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
80. The heat exchanger according to claim 76 wherein at least one of the plurality of microchannels has a width dimension within the range of and including 10 to 100 microns.
81. The heat exchanger according to claim 45 wherein the first layer is coupled to the heat source.
82. The heat exchanger according to claim 45 wherein the first layer is integrally formed to the heat source.
83. The heat exchanger according to claim 45 wherein the heat source is an integrated circuit.
84. The heat exchanger according to claim 45 further comprising a thermoelectric device positioned between the first layer and the heat source, wherein the thermoelectric device is electrically coupled to a power source.
85. The heat exchanger according to claim 84 wherein the thermoelectric device is integrally formed within the heat exchanger.
86. The heat exchanger according to claim 84 wherein the thermoelectric device is integrally formed within the heat source.
87. The heat exchanger according to claim 84 wherein the thermoelectric device is coupled to the heat exchanger and the heat source.
88. A method of manufacturing a heat exchanger configured to cool a heat source positioned along a plane, the method comprising the steps of:
a. providing a first layer configurable to be in contact with the heat source and to pass fluid along a heat conducting surface;
b. coupling a second layer to the first layer, wherein a first side of the second layer is in contact with the heat conducting surface and configured to pass fluid from the first layer therethrough; and
c. coupling a third layer to the first and second layers, wherein a second side of the second layer is in contact with the third layer.
89. The method of manufacturing according to claim 88 wherein the first layer further comprises a recess area having the heat conducting surface.
90. The method of manufacturing according to claim 88 wherein the heat exchanger includes at least one inlet port for channeling fluid to the first side and at least one outlet port for channeling fluid from the second side.
91. The method of manufacturing according to claim 90 wherein the first layer includes the at least one inlet port.
92. The method of manufacturing according to claim 90 wherein the first layer includes the at least one outlet port.
93. The method of manufacturing according to claim 90 wherein the third layer includes the at least one inlet port.
94. The method of manufacturing according to claim 90 wherein the third layer includes the at least one outlet port.
95. The method of manufacturing according to claim 90 wherein the at least one inlet port is positioned substantially parallel with respect to the plane.
96. The method of manufacturing according to claim 90 wherein the at least one inlet port is positioned substantially perpendicular with respect to the plane.
97. The method of manufacturing according to claim 90 wherein the at least one outlet port is positioned substantially parallel with respect to the plane.
98. The method of manufacturing according to claim 90 wherein the at least one outlet port is positioned substantially perpendicular with respect to the plane.
99. The method of manufacturing according to claim 89 wherein the recess area includes a plurality of fluid inlet grooves along the heat conducting surface, the fluid inlet grooves for channeling fluid from at least one inlet port to the second layer.
100. The method of manufacturing according to claim 88 wherein the fluid is in single phase flow conditions.
101. The method of manufacturing according to claim 88 wherein at least a portion of the fluid is in two phase flow conditions.
102. The method of manufacturing according to claim 88 wherein the first layer has a thickness dimension within the range of and including 0.3 to 0.7 millimeters.
103. The method of manufacturing according to claim 88 wherein an overhang dimension is within the range of and including 0 to 15 millimeters.
104. The method of manufacturing according to claim 88 wherein at least a portion of the fluid undergoes a transition between single and two phase flow conditions in the heat exchanger.
105. The method of manufacturing according to claim 88 wherein the first layer is made of a material having a thermal conductivity of at least 100 Wm-K.
106. The method of manufacturing according to claim 88 further comprising forming a plurality of pillars in a predetermined pattern along the interface layer.
107. The method of manufacturing according to claim 106 wherein at least one of the plurality of pillars has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
108. The method of manufacturing according to claim 106 wherein at least one of the plurality of pillars has a height dimension within the range of and including 50 microns and 2 millimeters.
109. The method of manufacturing according to claim 106 wherein at least two of the plurality of pillars are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
110. The method of manufacturing according to claim 106 wherein at least one of the plurality of pillars includes at least varying dimension along a predetermined direction.
111. The method of manufacturing according to claim 88 further comprising configuring at least a portion of the interface layer to have a roughened surface.
112. The method of manufacturing according to claim 88 wherein the second layer is made of a micro-porous structure.
113. The method of manufacturing according to claim 112 wherein the porous microstructure has a porosity within the range of and including 50 to 80 percent.
114. The method of manufacturing according to claim 112 wherein the porous microstructure has an average pore size within the range of and including 10 to 200 microns.
115. The method of manufacturing according to claim 112 wherein the porous microstructure has a height dimension within the range of and including 0.25 to 2.00 millimeters.
116. The method of manufacturing according to claim 88 further comprising forming a plurality of microchannels onto the first layer.
117. The method of manufacturing according to claim 116 wherein at least one of the plurality of microchannels has an area dimension within the range of and including (10 micron)2 and (100 micron)2.
118. The method of manufacturing according to claim 116 wherein at least one of the plurality of microchannels has a height dimension within the range of and including 50 microns and 2 millimeters.
119. The method of manufacturing according to claim 116 wherein at least two of the plurality of microchannels are separate from each other by a spacing dimension within the range of and including 10 to 150 microns.
120. The method of manufacturing according to claim 116 wherein at least one of the plurality of microchannels has a width dimension within the range of and including 10 to 100 microns.
121. The method of manufacturing according to claim 88 wherein the first layer is coupled to the heat source.
122. The method of manufacturing according to claim 88 wherein the first layer is integrally formed to the heat source.
123. The method of manufacturing according to claim 88 wherein the heat source is an integrated circuit.
124. The method of manufacturing according to claim 88 further comprising configuring a thermoelectric device between the first layer and the heat source, wherein the thermoelectric device is electrically coupled to a power source.
125. The method of manufacturing according to claim 124 wherein the thermoelectric device is integrally formed within the heat exchanger.
126. The method of manufacturing according to claim 124 wherein the thermoelectric device is integrally formed within the heat source.
127. The-method of manufacturing according to claim 124 wherein the thermoelectric device is coupled to the heat exchanger and the heat source.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing an insulated gate field effect transistor comprising:
forming a gate electrode on an insulating surface of a substrate;
forming a gate insulating film comprising silicon nitride layer and a silicon oxide layer over said gate electrode;
forming a semiconductor film comprising amorphous silicon on said gate insulating film successively after the formation of said gate insulating film without exposing said gate insulating film to air, said semiconductor film comprising hydrogen and having a portion to become a channel region of said transistor,
crystallizing said semiconductor film including said portion after the formation of said semiconductor film; and
forming source and drain regions with said channel region extending therebetween.
2. A method according to claim 1 wherein a concentration of oxygen is said semiconductor film is not higher than 1\xd71019 atomscm3.
3. A method of manufacturing an insulated gate field effect transistor comprising:
preparing a multi-chamber system having at least first and second chambers that can be airtightly isolated, respectively;
forming a gate electrode on an insulating surface of a substrate;
forming a gate insulating film comprising silicon nitride layer and a silicon oxide layer over said gate electrode in said first chamber;
transferring the substrate after forming said gate insulating film from said first chamber to said second chamber without exposing said gate insulating film to air;
forming a semiconductor film comprising amorphous silicon on said gate insulating film in said second chamber, said semiconductor film containing hydrogen and having a portion to become a channel region of said transistor;
crystallizing said semiconductor film including said portion after the formation of said semiconductor film; and
forming source and drain regions with said channel region extending therebetween.
4. A method of manufacturing an insulated gate field effect transistor having a channel region comprising a single semiconductor layer comprising:
forming an insulating film comprising silicon nitride layer and a silicon oxide layer over a substrate;
forming a semiconductor film comprising amorphous silicon on said insulating film successively after the formation of said insulating film without exposing said insulating film to air, said semiconductor film containing hydrogen and having a portion to become a channel region of said transistor,
crystallizing said semiconductor film including said portion after the formation of said semiconductor film.
5. A method of manufacturing an insulated gate field effect transistor having a channel region comprising a single semiconductor layer comprising:
preparing a multi-chamber system having at least first and second chambers that can be airtightly isolated, respectively;
forming an insulating film comprising silicon nitride layer and a silicon oxide layer over a substrate in said first chamber;
transferring the substrate after forming said insulating film from said first chamber to said second chamber without exposing said insulating film;
forming a semiconductor film comprising amorphous silicon on said insulating film in said second chamber, said semiconductor film containing hydrogen and having a portion to become a channel region of said transistor;
crystallizing said semiconductor film including said portion after the formation of said semiconductor film.
6. A method of manufacturing an insulated gate field effect transistor comprising:
preparing a multi-chamber system having at least first, second and third chambers wherein said third chamber is commonly connected to said first and second chambers through valves;
forming a gate electrode on an insulating surface of a substrate;
forming a gate insulating film comprising silicon nitride layer and a silicon oxide layer over said gate electrode in said first chamber;
transferring the substrate after forming said gate insulating film from said first chamber to said second chamber through said third chamber;
forming a semiconductor film comprising amorphous silicon on said gate insulating film in said second chamber, said semiconductor film containing hydrogen and having a portion to become a channel region of said transistor;
crystallizing said semiconductor film including said portion after the formation of said semiconductor film.
7. The method of manufacturing an insulated gate field effect transistor of claim 1 wherein said semiconductor film contains hydrogen at a concentration not higher than 5 atom %.
8. The method of manufacturing an insulated gate field effect transistor of claim 1 wherein said semiconductor film has an electron mobility 50 to 300 cm2Vs.
9. The method of manufacturing an insulating gate field effect transistor of claim 1 wherein said semiconductor film after the crystallization has an average diameter of crystals in the crystallized semiconductor film within 50 to 200 angstrom based on Raman spectra analysis.
10. The method of manufacturing an insulating gate field effect transistor of claim 1 wherein the crystallization of the semiconductor film is conducted by heating at 450 to 700\xb0 C.
11. The method of manufacturing an insulating gate field effect transistor of claim 1 wherein the crystallization of the semiconductor film is conducted by irradiation of laser.
12. The method of manufacturing an insulating gate field effect transistor of claim 1 wherein the crystallization of the semiconductor film is conductor by irradiation of a halogen lamp.
13. The method of manufacturing an insulating gate field effect transistor of claim 1 wherein the step of formation of said source and drain regions is performed after said step of crystallizing said semiconductor film.
14. The method of manufacturing an insulated field effect transistor of claim 3, wherein said semiconductor film contains hydrogen at a concentration not higher than 5 atom %.
15. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein said semiconductor film has an electron mobility 50 to 300 cm2Vs.
16. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein said semiconductor film after the crystallization has an average diameter of crystals in the crystallized semiconductor film within 50 to 200 angstrom based on Raman spectra analysis.
17. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein the crystallization of the semiconductor film is conducted by heating at 450 to 700\xb0 C.
18. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein the crystallization of the semiconductor film is conducted by irradiation of laser.
19. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein the crystallization of the semiconductor film is conducted by irradiation of a halogen lamp.
20. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein said semiconductor film contains oxygen in a concentration not higher than 7\xd71019 atomscm3.
21. The method of manufacturing an insulating gate field effect transistor of claim 3 wherein the step of formation of said source and drain regions is performed after said step of crystallizing said semiconductor film.
22. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein said semiconductor film contains hydrogen at a concentration not higher than 5 atom %.
23. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein said semiconductor film has an electron mobility 50 to 300 cm2Vs.
24. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein said semiconductor film after the crystallization has an average diameter of crystals in the crystallized semiconductor film within 50 to 200 angstrom based on Raman spectra analysis.
25. The method of manufacturing an insulated gate field effect transistor of claim 4 wherein the crystallization of the semiconductor film is conducted by heating at 450 to 700\xb0 C.
26. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein the crystallization of the semiconductor film is conducted by irradiation of laser.
27. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein the crystallization of the semiconductor film is conducted by irradiation of a halogen lamp.
28. The method of manufacturing an insulating gate field effect transistor of claim 4 wherein said semiconductor film contains oxygen in a concentration not higher than 7\xd71019 atomscm3.
29. The method of manufacturing an insulating gate field effect transistor of claim 4 farther comprising a step of forming source and drain regions with said channel region extending therebetween after said step of crystallizing said semiconductor film.
30. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein said semiconductor film contains hydrogen at a concentration not higher than 5 atom %.
31. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein said semiconductor film has an electron mobility 50 to 300 cm2Vs.
32. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein said semiconductor film after the crystallization has an average diameter of crystals in the crystallized semiconductor film within 50 to 200 angstrom based on Raman spectra analysis.
33. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein the crystallization of the semiconductor film is conducted by heating at 450 to 700\xb0 C.
34. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein the crystallization of the semiconductor film is conducted by irradiation of laser.
35. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein the crystallization of the semiconductor film is conducted by irradiation of a halogen lamp.
36. The method of manufacturing an insulating gate field effect transistor of claim 5 wherein said semiconductor film contains oxygen in a concentration not higher than 7\xd71019 atomscm3.
37. The method of manufacturing an insulating gate field effect transistor of claim 5 further comprising a step of forming source and drain regions with said channel region extending therebetween after said step of crystallizing said semiconductor film.
38. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein said semiconductor film contains hydrogen at a concentration not higher than 5 atom %.
39. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein said semiconductor film has an electron mobility 50 to 300 cm2Vs.
40. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein said semiconductor film after the crystallization has an average diameter of crystals in the crystallized semiconductor film within 50 to 200 angstrom based on Raman spectra analysis.
41. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein the crystallization of the semiconductor film is conducted by heating at 450 to 700\xb0 C.
42. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein the crystallization of the semiconductor film is conducted by irradiation of laser.
43. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein the crystallization of the semiconductor film is conducted by irradiation of a halogen lamp.
44. The method of manufacturing an insulating gate field effect transistor of claim 6 wherein said semiconductor film contains oxygen in a concentration not higher than 7\xd71019 atomscm3.
45. The method of manufacturing an insulating gate field effect transistor of claim 6 further comprising a step of forming source and drain regions with said channel region extending therebetween after said step of crystallizing said semiconductor film.