1-14. (canceled)
15. A method of inhibiting leukemia cell growth in a host, comprising:
administering into said host a leukemia cell growth-inhibiting effective amount of a composition comprising:
(1) an anti-CCL25 antibody, a fragment of an anti-CCL25 antibody, an anti-CCR9 antibody, or a fragment of an anti-CCR9 antibody; and
(2) a pharmaceutically acceptable carrier.
16. The method of claim 15, wherein said anti-CCL25 antibody or said anti-CCR9 antibody is a human antibody.
17. The method of claim 15, wherein said anti-CCL25 antibody or said anti-CCR9 antibody is a humanized antibody.
18. The method of claim 15, wherein said anti-CCL25 antibody or said anti-CCR9 antibody is a chimeric antibody.
19. The method of claim 15, wherein said composition comprises both said anti-CCL25 antibody and said anti-CCR9 antibody.
20. The method of claim 15, wherein said pharmaceutically acceptable carrier comprises liposomes.
21. The method of claim 15, wherein said pharmaceutically acceptable carrier comprises microspheres.
22. The method of claim 15, wherein said composition is administered intravenously.
23. The method of claim 15, wherein said composition is administered intramuscularly.
24. The method of claim 15, wherein said anti-CCL25 antibody, a fragment of an anti-CCL25 antibody, an anti-CCR9 antibody, or a fragment of an anti-CCR9 antibody is administered at a dose range of 0.01-1000 mgkgday.
25. The method of claim 15, wherein said anti-CCL25 antibody or said anti-CCR9 antibody is administered at a dose range of 0.1-100 mgkgday.
26. The method of claim 15, wherein said pharmaceutically acceptable carrier is saline.
27. The method of claim 26, wherein said saline is buffered saline.
28. The method of claim 15, wherein said pharmaceutically acceptable carrier is glucose in saline.
29. The method of claim 15, wherein said composition further comprises an antibody, or a fragment of an antibody, that binds to a chemokine or chemokine receptor selected from the group consisting of CCL1, CCL4, CCL17, CCL19, CCL21, CCL22, CXCL12, CCR7, CCR8, CXCR4.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor chip for process monitoring of semiconductor fabrication, comprising:
a plurality of arrays further comprising:
a plurality of diodes, each said diode being formed in the chip, each said diode being associated with a stack comprising at least one horizontal interconnect, said stack and said diode connected in series to form a diode stack combination,
wherein the horizontal interconnect comprises a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.
2. The semiconductor chip according to claim 1, wherein a silicide layer is formed on top of the complimentary doped polysilicon.
3. The semiconductor chip according to claim 1, wherein the silicide layer is TiS2, CoSi2, NiSi, or WSi2.
4. The semiconductor chip according to claim 2, wherein the salicided polysilicon is contacted by first and second vias arranged on top of said silicide layer, wherein the first via is located above a p+ doped polysilicon section and the second via is located above a n+ doped polysilicon section.
5. The semiconductor chip according to claim 1, wherein the stack further comprises at least one vertical interconnect comprising a plurality of vias and metal wires.
6. A test system comprising a semiconductor according to claim 1, and further comprising:
a plurality of control mechanisms for addressing said diodes wherein said control mechanisms comprise:
a device for applying a relatively high or low voltage to a plurality of columns of said diode stack combinations in said array, connected at a first end of said diode stack combination; and
a device for applying a relatively high or low voltage to a plurality of rows of said diode stack combinations in said array, connected at a second end of said diode stack combination.
7. The system of claim 6, wherein the control mechanisms are inverters.
8. The system of claim 6, wherein the diodes are formed by a first p-type semiconductor deposition into an n-type well which is arranged within a p-type substrate,
said chip further comprising a plurality of electrical connections for each said diode comprising deposition of a second p-type semiconductor into said p-type substrate; and
said arrays further comprising a plurality of p-n-p parasitic transistors comprised of said electrical connections, said p-type substrate, said n-type well, and said first p-type semiconductor depositions.
9. The system of claim 8, wherein said parasitic transistors share a physical location with said diodes, and said parasitic transistors and said diodes are connected in parallel.
10. The system of claim 6, wherein a plurality of p-type semiconductor regions are deposited adjacent to each said diode, said p-type semiconductor regions connected to the terminal of a transistor adjacent to said diode in the substrate of said chip.
11. The system of claim 10, wherein the p-type semiconductor regions adjacent to each diode in a said array are connected together.
12. The system of claim 10, wherein the p-type semiconductors regions are connected to a first voltage, said voltage having a lower potential than said high voltage applicable to a column of diode stack combinations.
13. A system for process monitoring of semiconductor fabrication, comprising:
a semiconductor chip further comprising:
a plurality of arrays further comprising:
a plurality of diodes, each said diode being formed in the chip, each said diode being associated with a stack comprising at least one metal contact and at least one horizontal interconnect, wherein the horizontal interconnect comprises a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode, said stack and said diode connected in series to form a diode stack combination;
a plurality of control mechanisms for addressing said diodes wherein said control mechanisms comprise:
a device for applying a relatively high or low voltage to a plurality of columns of said diode stack combinations in said array, connected at a first end of said diode stack combination;
a device for applying a relatively high or low voltage to a plurality of rows of said diode stack combinations in said array, connected at a second end of said diode stack combination, and
wherein the device is further operable to measure a current through said diode stack combination.
14. The system according to claim 13, wherein the stack further comprises at least one vertical interconnect comprising a plurality of vias and metal wires.
15. The system of claim 13, wherein the control mechanisms are inverters.
16. The system of claim 13, wherein the diodes are formed by a p-n transition within said semiconductor chip formed by a first p-type semiconductor area in an n-type well, wherein the n-type well is arranged in a p-type substrate;
said chip further comprising a plurality of electrical connections for each said diode comprising deposition of a second p-type semiconductor into said p-type substrate; and
said arrays further comprising a plurality of p-n-p parasitic transistors comprised of said electrical connections, said p-type substrate, said n-type well, and said first p-type semiconductor depositions.
17. The system of claim 16, wherein said parasitic transistors share a physical location with said diodes, and said parasitic transistors and said diodes are connected in parallel.
18. The system of claim 13, wherein said semiconductor chip further comprises a plurality of p-type semiconductor regions arranged adjacent to each said diode, said p-type semiconductor regions connected to the terminal of a transistor adjacent to said diode in the substrate of said chip.
19. The system of claim 18, wherein the p-type semiconductor regions adjacent to each diode in a said array are connected together.
20. The system of claim 18, wherein the p-type semiconductors regions are connected to a first voltage, said voltage having a lower potential than said high voltage applicable to a column of diode and stack combinations.