1. An integrated structure for microfluidic analysis and sorting comprising:
a cartridge, the cartridge comprising
an optical window,
a plurality of reservoirs, including at least:
a sample reservoir,
a fluid reservoir,
a waste reservoir, and
a target collection reservoir,
a chip, the chip including at least:
a sample inlet channel, the cell inlet channel being fluidically coupled to the sample reservoir,
one or more fluid inlet channels, the fluid inlet channels being fluidically coupled to the fluid reservoir,
a detection region,
a branched sorting region, and
at least two outlet channels including at least a waste channel and a target channel, waste channel being fluidically coupled to the waste reservoir and the target channel being coupled to the target collection reservoir,
the chip being disposed adjacent the optical window, and
a lid, the lid including at least:
a pneumatic pressure port, the port having an inlet and being coupled to at least one of the sample reservoir and the fluid reservoir, and
a filter disposed between the inlet of the pneumatic pressure port and at least one of the sample reservoir and the fluid reservoir,
a detector adapted to detect cells of a given state and to generate a signal in response thereto, and
a lateral force switch coupled to the detector and actuatable in response to the signal, the lateral force switch comprising a laser spot configured to be translated down the length of the detection region at an angle relative to a flow stream through the detection region;
whereby when a cell of a given state is detected, the lateral force switch is activated to sweep the laser spot alongside the cell as it flows to provide a lateral force on the cell so as to move the cell such that it selectively exits into the one of the at least two outlet channels.
2. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the sample reservoir is conical.
3. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the sample reservoir is tapered.
4. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the sample reservoir further includes an insert.
5. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the insert is a polypropylene insert.
6. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid is plastic.
7. The integrated structure for microfluidic analysis and sorting of claim 6 wherein the lid is acrylic plastic.
8. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid includes separate pneumatic pressure ports for the sample reservoir and the fluid reservoir.
9. The integrated structure for microfluidic analysis and sorting of claim 8 wherein the lid includes a pneumatic pressure port for the target collection reservoir.
10. The integrated structure for microfluidic analysis and sorting of claim 8 wherein the lid includes a pneumatic pressure port for the waste reservoir.
11. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid includes a pneumatic pressure port for the target collection reservoir.
12. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid includes a pneumatic pressure port for the waste reservoir.
13. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid provides optical access to the reservoirs.
14. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the lid includes snap-on attachments to couple to the cartridge.
15. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the filter is gas permeable.
16. The integrated structure for microfluidic analysis and sorting of claim 15 wherein the filter is fluid impermeable.
17. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the filter is fluid impermeable.
18. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the filter is a polypropylene filter.
19. The integrated structure for microfluidic analysis and sorting of claim 1 wherein curable adhesive is disposed between the chip and the cartridge.
20. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the adhesive is UV curable.
21. The integrated structure for microfluidic analysis and sorting of claim 1 further including a bonding sheet between the chip and the cartridge.
22. The integrated structure for microfluidic analysis and sorting of claim 21 wherein the bonding sheet is a pressure sensitive adhesive.
23. The integrated structure for microfluidic analysis and sorting of claim 1 wherein optical access to the chip is provided through the optical window and through the reverse side of the chip.
24. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the sample reservoir is adapted to contain from 10 to 30 microliters.
25. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the fluid reservoir is adapted to contain 500 to 1,500 microliters.
26. The integrated structure for microfluidic analysis and sorting of claim 1 further including a gasket between the lid and cartridge.
27. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the waste reservoir contains non-target materials.
28. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the waste reservoir contains excess fluid.
29. The integrated structure for microfluidic analysis and sorting of claim 1 wherein the chip and cartridge comprise two separate structures.
30. A method for cell sorting in a device having an inlet, a fluidically coupled channel, and at least two fluidically coupled outputs, comprising the steps of:
receiving a cell in a fluidic medium at an inlet,
flowing the cell through a fluidic channel,
subjecting the cell to a bias flow resulting in collection in a first reservoir,
identifying a cell to be sorted through application of a lateral force into a second reservoir, and
applying a lateral force on the cell, the lateral force comprising a laser spot configured to be translated at a non-zero angle down the fluidic channel toward the at least two outputs and characterized in that the lateral force is a non-trapping force and in that the lateral force is moved alongside a selected cell as it flows down the fluidic channel, thereby increasing the total interaction time between the lateral force and the cell, whereby the cell selectively exits into the outlets.
31. The method for cell sorting of claim 30 wherein the laser illumination is moved linearly along the channel in proximity to the cell as it flows through the channel.
32. The method for cell sorting of claim 30 wherein the laser illumination is moved diagonally along the channel in proximity to the cell as it flows through the channel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of:
providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said top metal pads in recesses and planar with a first insulating layer on said substrate;
forming a second insulating layer over said top metal pads and with openings to top surface of said top metal pads;
forming elevated bond pads in said openings and extending above surface of said second insulating layer, with exposed sidewalls on said elevated bond pads;
forming sidewall spacers on said exposed sidewalls; and
forming an under-bump material barrier layer selectively on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu.
2. The method of claim 1, wherein said semiconductor chips have integrated circuits (devices) electrically connected to said top metal pads.
3. The method of claim 1, wherein said top metal pads are formed by depositing a conformal barrier layer of TaTaN and filling said recesses with copper.
4. The method of claim 1, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide-silicon nitride-silicon oxide and is deposited to a thickness of between 1000 and 20000 Angstroms.
5. The method of claim 1, wherein said elevated bond pads are formed by:
depositing a conformal TaTaN barrier layer and anisotropically etching back to leave said TaTaN barrier layer on the sidewalls of said openings while exposing the top surface of said second insulating layer and top surface of said top metal pads in said openings; and
electroless plating copper selectively in said openings, and said elevated bond pads have a height of at least greater than 800 Angstroms above top surface of said second insulating layer.
6. The method of claim 1, wherein said sidewalls spacers are formed by depositing a conformal insulating layer of silicon oxide or silicon nitride formed to a thickness of between about 100 and 1000 Angstroms, and anisotropically etching back said insulating layer to top surface of said elevated bond pads.
7. The method of claim 1, wherein said under-bump material barrier layer is deposited and patterned using a photoresist mask to leave portions on top surface of said elevated bond pads.
8. A method for fabricating elevated bond pads on semiconductor chips comprising the steps of:
providing a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads in recesses and planar with a first insulating layer on said substrate;
forming a second insulating layer over said top metal pads and with openings to top surface of said top metal pads;
depositing a conformal barrier layer and an electrically conducting layer and patterning to form elevated bond pads in and aligned over said openings and extending above the surface of said second insulating layer with exposed first sidewalls on said elevated bond pads;
patterning said elevated bond pads by partial anisotropically etching to further reduce the top surface area and form second sidewalls on said elevated bond pads;
forming sidewall spacers on said exposed first and second sidewalls; and
forming an under-bump material barrier layer selectively on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu.
9. The method of claim 8, wherein said semiconductor chips have integrated circuits (devices) electrically connected to said top metal pads.
10. The method of claim 8, wherein said top metal pads are formed by depositing a conformal barrier layer of TaTaN and filling said recesses with copper.
11. The method of claim 8, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide-silicon nitride-silicon oxide and is deposited to a thickness of between 1000 and 20000 Angstroms.
12. The method of claim 8, wherein said elevated bond pads are formed by:
depositing a conformal TaTaN barrier layer and depositing an aluminum alloy to fill said openings;
using a first photoresist mask and anisotropically etching to form said elevated bond pads over said openings and to form said first sidewalls on said elevated bond pads; and
using a second photoresist mask and partially anisotropically etching to reduce the top surface of said elevated bond pads and to form said second sidewalls on said elevated bond pads, and said elevated bond pads have a height of at least greater than 800 Angstroms above the top surface of said second insulating layer.
13. The method of claim 8, wherein said sidewall spacers are formed by depositing a conformal insulating layer of silicon oxide or silicon nitride formed to a thickness of between about 100 and 1000 Angstroms, and anisotropically etching back to top surface of said elevated bond pads.
14. The method of claim 8, wherein said under-bump material barrier layer is deposited and patterned using a photoresist mask to leave portions on the top surface of said elevated bond pads.
15. Elevated bond-pads on semiconductor chips comprised of:
a semiconductor substrate having an array of said semiconductor chips each with an array of top metal pads, said metal pads in recesses and planar with a first insulating layer on said substrate;
a second insulating layer over said top metal pads and with openings to top surface of said top metal pads;
said elevated bond pads in said openings and extending above the surface of said second insulating layer, with sidewalls on said elevated bond pads;
sidewall spacers on said sidewalls; and
an under-bump material barrier layer on the top surface of said elevated bond pads wherein said under-bump material barrier layer is a multilayer of an adhesion layer selected from the group consisting of TiW, Cr, and Al, a diffusion barrier layer selected from the group consisting of CrCu and, Ni(V), and a solder-wetting layer selected from the group consisting of Au, Pt, Pd, Ag, Sn, and Cu.
16. The structure of claim 15, wherein said second insulating layer is a dual-layer of silicon oxide and silicon nitride or a tri-layer of silicon oxide SiNSiO2 and has a thickness of between 1000 and 20000 Angstrom.
17. The structure of claim 15, wherein said elevated bond pads are copper formed by electroless plating and have a height of at least greater than 800 Angstroms above the top surface of said second insulating layer.
18. The structure of claim 15, wherein said elevated bond pads are an aluminum alloy and have a height of at least greater than 800 Angstroms above the top surface of the second insulating layer and said elevated bond pads are recessed and have second sidewalls on said elevated bond pads to reduce the top surface areas of said elevated bond pads, and wherein said sidewall spacers are silicon oxide or silicon nitride.