1. A sequence control circuit comprising:
a program counter control section which decodes, in an n-th clock cycle, a sequence control instruction that is executed in the n-th clock cycle, determines, in the n-th clock cycle, a program counter signal for specifying a sequence control instruction to be executed in an (n+1)th clock cycle, and outputs, in the (n+1)th cycle, the determined program counter signal as an instruction memory address; and
an instruction memory section which reads, in the n-th cycle, said sequence control instruction to be executed in the (n+1)th clock cycle based on a program counter signal for specifying said sequence control instruction that is executed in the n-th clock cycle, and outputs, in the (n+1)th clock cycle, the read sequence control instruction to said program counter control section.
2. A sequence control circuit according to claim 1, wherein
said instruction memory section is accessed by said instruction memory address sent from said program counter control section, and is provided with a first storage area for storing a first sequence control instruction contained in the next line of the line specified by said instruction memory address and a second storage area for storing a second sequence control instruction contained in the line of the jump target of the instruction specified by said instruction memory address for each value of said instruction memory address, and
the circuit is further provided with a selector which selects either one of said first and second sequence control instructions that are read out from said instruction memory section in accordance with said instruction memory address, and
said program counter control section outputs not only said instruction memory address but also a selection signal whose level is determined by whether said sequence control instruction selected by said selector causes a jump operation to said selector.
3. A sequence control circuit according to claim 2, wherein when the selected sequence control instruction causes a jump operation, said program counter control section outputs a selection signal for directing said selector to select said second sequence control instruction, or otherwise when the selected sequence control instruction does not cause a jump operation, said program counter control section outputs a selection signal for directing said selector to select said first sequence control instruction.
4. A sequence control circuit according to claim 2, wherein
said instruction memory section includes first and second registers which hold said first and second sequence control instructions that are read from said first and second storage areas, respectively, and
said selector selects either one of outputs from said first and second registers in accordance with said selection signal.
5. A sequence control circuit according to claim 2, wherein said program counter control section includes a third register which holds said program counter signal for specifying a sequence control instruction to be executed in the (n+1)th clock cycle, and a fourth register which holds said selection signal.
6. A sequence control circuit according to claim 2, wherein said instruction memory section includes a first register which holds the sequence control instruction selected by said selector to output that to said program counter control section.
7. A sequence control circuit according to claim 2, wherein said program counter control section includes a second register which holds said program counter control signal for specifying the sequence control instruction to be executed in said (n+1)th clock cycle, and directly outputs said selection signal to said selector.
8. A sequence control circuit according to claim 1, wherein the circuit is installed in a semiconductor testing apparatus which generates test patterns for testing a semiconductor device based on said instruction memory address.
9. A sequence control circuit according to claim 1, wherein the program counter signal has a value specifying a sequence control instruction to be executed.
10. A semiconductor testing apparatus comprising:
a pattern memory which stores pattern generating instructions for testing a semiconductor device;
a sequence control circuit which supplies an instruction memory address to said pattern memory in order to control the output sequence of the pattern generating instructions that are read out from said pattern memory;
a pattern generating circuit which generates test patterns supplied to said semiconductor device and expectation patterns in accordance with said pattern generating instructions that are output from said pattern memory; and
a determination circuit which determines the quality of said semiconductor device based on said expectation patterns and signals that are sent from said semiconductor device in accordance with said test patterns,
wherein said sequence control circuit comprising:
a program counter control section which decodes, in an n-th clock cycle, a sequence control instruction that is executed in the n-th clock cycle, determines, in the n-th clock cycle, a program counter signal for specifying a sequence control instruction to be executed in an (n+1)th clock cycle, and outputs, in the (n+1)th clock cycle, the determined program counter signal as said instruction memory address; and
an instruction memory section which reads, in the n-th cycle, said sequence control instruction to be executed in the (n+1)th clock cycle based on a program counter signal for specifying said sequence control instruction that is executed in the n-th clock cycle, and outputs, in the (n+1)th clock cycle, the read sequence control instructions to said program counter control section.
11. A semiconductor testing apparatus according to claim 10, wherein the program counter signal has a value specifying a sequence control instruction to be executed.
12. A method for operating a sequence control circuit including a program counter control section and instruction memory section, said method comprising:
receiving and decoding, at the program counter control section in an n-th clock cycle, a sequence control instruction that is executed in the n-th clock cycle;
determining, at the program counter control section in the n-th clock cycle, a program counter signal for specifying a sequence control instruction to be executed in an (n+1)th clock cycle;
outputting, from the program counter control section in the (n+1)th clock cycle, the determined program counter signal for the (n+1)th clock cycle as an instruction memory address;
reading, at the instruction memory section in the n-th clock cycle, the sequence control instruction to be executed in the (n+1)th clock cycle based on a program counter signal for specifying the sequence control instruction that is executed in the n-th clock cycle; and
outputting, from the instruction memory section in the (n+1)th clock cycle, the read sequence control instruction to the program counter control section.
13. A method according to claim 12, wherein the program counter signal has a value specifying a sequence control instruction to be executed.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system comprising:
a distributed network; and
plurality of node devices connected to the distributed network, each node device having local measurements that are independent and identical distributed samples of a random variable, wherein each node device uses gossip-based distributed kernel density estimation to estimate an unknown distribution from the distributed samples using kernel density estimation comprising:
obtaining the random values with an unknown distribution from each of the node devices;
maintaining a local kernel set of each of the node devices;
selecting from the plurality of node devices, a random node as a gossip target node;
exchanging kernels from the gossip target node with each one of the remaining node devices;
merging kernels with target node and kernels of each of the remaining nodes devices;
determining whether the merged kernels exceed the resources of a particular node device of the remaining node devices; and
performing a data reduction if the merged kernels exceed the resources of the particular node device.
2. The system of claim 1, wherein the node devices are one or more of the following: a personal computer, a sensor, a peer, or an agent.
3. The system of claim 1, wherein the kernel density estimation is defined as:
f
^
\u2061
(
x
)
=
\u2211
i
=
1
N
\u2062
w
i
\u2062
K
H
i
\u2061
(
x
–
x
i
)
,
4. The system of claim 1, wherein each node receives a probability density function by collecting information and approximating a global kernel density estimation through a gossip process.
5. The system of claim 1, wherein each node device receives a unique and increasing round identifier attached to a gossip message that distinguishes gossip messages of each round.
6. The system of claim 1, wherein a node device joins the distributed kernel density estimation when the node device receives a round identifier having a value greater than a value of a current round.
7. A method to estimate kernel density comprising of:
obtaining a sample random value with an unknown distribution from each node of a plurality of nodes in a computing system;
maintaining a local kernel set of each of the nodes;
selecting from the plurality of nodes, a random node as a gossip target node;
exchanging kernels from the gossip target node with each one of the remaining nodes;
merging kernels with target node and kernels of each of the remaining nodes;
determining whether the merged kernels exceed the resources of a particular node of the remaining nodes; and
performing a data reduction, if the merged kernels exceed the resources of the particular node.
8. The method of claim 7 further comprising updating a kernel set of each of the plurality of nodes.
9. The method of claim 7 further comprising determining a number of gossip cycles that have been completed for the computing system.
10. The method of claim 9, wherein the number of gossip cycles is used to calculate a global kernel density estimate, when the number of gossip cycles is completed.
11. The method of claim 9, wherein a local kernel estimate is performed at each of the nodes, if the number of gossip cycles is not completed.
12. The method of claim 7, wherein a passive exchange is performed between the random node and one or more of the remaining nodes.
13. The method of claim 7, wherein a local density estimation at each of the nodes is defined by:
f
^
\u2061
(
x
)
=
\u2211
i
=
1
N
\u2062
w
i
\u2062
K
H
i
\u2061
(
x
–
x
i
)
,
14. The method of claim 7, wherein resource limitation of each of the nodes determines the exchange of kernels between the nodes.
15. A method of data reduction in a computing system comprising of:
receiving a value representing a kernel set of a number of kernels in a node of the computing system;
receiving a value representing a value of compressed kernel set of the node;
determining whether the value representing the kernel set is greater than the value of the compressed kernel set;
determining two kernels of the node form the kernel set if the value representing the kernel set is greater than the value of the compressed kernel set, wherein the centers of the two determined kernels are selected having minimal distance between one another;
merging the two kernels into a new kernel;
removing the two kernels form the kernel set; and
creating a kernel set.
16. The method of claim 15, wherein the value representing the kernel set of the number of kernels in the node is represented by a temporary variable value.
17. The method of claim 15, wherein the merging is performed when the determining whether the value representing the kernel set is greater than the value of the compressed kernel set is determined to be not true.
18. The method of claim 15, wherein the merging is performed by to following:
w
j
\u2032
=
w
j
1
+
w
j
2
x
j
\u2032
=
w
j
1
\u2062
x
j
1
+
w
j
2
\u2062
x
j
2
w
j
1
+
w
j
2
H
j
\u2032
=
w
j
1
\u2061
(
H
j
1
+
x
j
\u2062
\u2062
1
\u2062
x
j
\u2062
\u2062
1
T
)
+
w
j
2
\u2061
(
H
j
2
+
x
j
2
\u2062
x
j
2
T
)
w
j
1
+
w
j
2
–
x
j
\u2032
\u2062
x
j
\u2032
\u2062
\u2062
T
19. The method of claim 15, wherein the number of iterations performed equals the difference between the value representing the kernel set of the number of kernels in the node and the value representing the compressed kernel set of the node.
20. The method of claim 15 further comprising outputting a kernel set of kernels approximating an original density estimate.