1. A method of processing data in a stateful protocol processing system configured to process multiple flows of messages, said method comprising:
receiving a first plurality of messages of a first of said flows, said first of said flows comporting with a first stateful protocol;
assigning a first protocol processing core to process event information derived from said first plurality of messages;
setting a first flow timer associated with said first of said flows;
generating a first timeout expiration event upon expiration of said first flow timer; and
forwarding said first timeout expiration event to said first protocol processing core;
storing a first flow state associated with said first of said flows in a common memory;
checking out said first flow state to a first local memory associated with said first protocol processing core;
maintaining a plurality of timers associated with said first of said flows within said common memory; and
storing values of said plurality of timers within a timer cache upon said checking out of said first flow state.
2. The method of claim 1 further including:
setting a second flow timer associated with a second of said flows;
generating a second timeout expiration event upon expiration of said second flow timer; and
forwarding said second timeout expiration event to a second protocol processing core.
3. The method of claim 1 further including retrieving said first flow state associated with said first of said flows in response to said first timeout expiration event.
4. The method of claim 1 further including providing said first flow state to said first protocol processing core.
5. The method of claim 1 wherein a plurality of timers are associated with said first of said flows, said method further including issuing timer expiration events upon expiration of ones of said plurality of timers.
6. The method of claim 5 further including inhibiting issuance of said timer expiration events subsequent to said checking out of said first flow state.
7. The method of claim 1 further including decrementing or otherwise modifying said values of said plurality of timers within said timer cache.
8. The method of claim 1 further including modifying a state of said first of said flows upon generation of said first timeout expiration event.
9. A method of processing data in a stateful protocol processing system configured to process multiple flows of messages, said method comprising:
receiving a first plurality of messages of a first of said flows, said first of said flows comporting with a first stateful protocol;
assigning a first protocol processing core to process event information derived from said first plurality of messages;
storing values of a plurality of timers associated with said first of said flows, said first protocol processing core setting a reset bit associated with one of said plurality of timers; and
adjusting a value of said one of said plurality of timers in response to said setting of said reset bit;
storing a first flow state associated with said first of said flows in a common memory;
checking out said first flow state to a first local memory associated with said first protocol processing core;
maintaining said plurality of timers associated with said first of said flows within said common memory; and
storing values of said plurality of timers within a timer cache upon said checking out of said first flow state.
10. The method of claim 9 further including:
generating a first timeout expiration event upon expiration of said one of said plurality of timers; and
forwarding said first timeout expiration event to said first protocol processing core.
11. The method of claim 10 further including:
retrieving a first flow state associated with said first of said flows in response to said first timeout expiration event; and
providing said first flow state to said first protocol processing core.
12. A stateful protocol processing apparatus configured to process multiple flows of messages, said apparatus comprising:
a first protocol processing core;
a common memory;
an input module configured to receive a first plurality of messages of a first of said flows, said first of said flows comporting with a first stateful protocol;
a dispatcher operative to assign said first protocol processing core to process event information derived from said first plurality of messages, said dispatcher storing a first flow state associated with said first of said flows in said common memory; and
a lookup controller configured to generate a first timeout expiration event upon expiration of a first flow timer associated with said first of said flows, said lookup controller forwarding said first timeout expiration event to said dispatcher, said lookup controller checking out said first flow state to a first local memory associated with said first protocol processing core, said lookup controller including a timer control unit configured to maintain a plurality of timers associated with said first of said flows within said common memory, wherein said lookup controller stores values of said plurality of timers within a timer cache upon said checking out of said first flow state.
13. The apparatus of claim 12 further including a flow director unit disposed to maintain a flow state table having a plurality of entries corresponding to said multiple flows, said lookup controller creating, in response to said first timeout expiration event, a first entry within said flow director unit corresponding to said first of said flows.
14. The apparatus of claim 13 wherein said flow director unit transitions said first entry out of a timer state into a different state in response to receipt of a service timer command associated with servicing of said timeout expiration event.
15. The apparatus of claim 12 wherein said dispatcher is operative to service said timeout expiration event by requesting said lookup controller to retrieve said first flow state from said common memory.
16. The apparatus of claim 15 wherein said lookup controller is operative to provide said first flow state and said timeout expiration event to said first protocol processing core.
17. The apparatus of claim 12 wherein said lookup controller is operative to decrement or otherwise modify ones of said values of said plurality of timers within said timer cache.
18. The apparatus of claim 12 further including a second protocol processing core, said dispatcher being operative to assign said second protocol processing core to process event information derived from a second plurality of messages of a second of said flows.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A logic circuit for controlling the read latency time of a memory circuit, comprising:
a first circuit for producing a plurality of values derived from a read enable signal, each value representative of the read enable signal delayed by a predetermined period of time; and
a second circuit for selecting one of said plurality of values in response to at least one control signal to enable a read operation.
2. The logic circuit of claim 1 wherein said first circuit includes a register comprised of a plurality of series connected flip-flops through which the read enable signal propagates, said plurality of values being available at output terminals of said flip-flops.
3. The logic circuit of claim 2 wherein said flip-flops are clocked with a clock signal that is twice the frequency of an externally supplied clock signal.
4. The logic circuit of claim 2 wherein said second circuit includes a plurality of logic gates each responsive to one of said flip-flops and said at least one control signal.
5. The logic circuit of claim 4 wherein said circuit includes seven series connected flip-flops and eight logic gates, and wherein each of said eight logic gates is responsive to each of three control signals and one of the values of the read enable signal.
6. A logic circuit for controlling the read latency time of a memory circuit comprising:
a signal generation circuit for generating a read enable signal;
a delay circuit for receiving said read enable signal and for producing a plurality of values of said read enable signal each delayed by a predetermined period of time; and
a multiplexer for selecting one of said plurality of values in response to at least one control signal.
7. The logic circuit of claim 6 additionally comprising a buffer enable register connected to the output of said multiplexer.
8. The logic circuit of claim 7 additionally comprising an every-edge register, the output of said register gated with the output of said multiplexer.
9. The logic circuit of claim 6 wherein said delay circuit includes a plurality of series connected flip-flops.
10. The logic circuit of claim 6 wherein said signal generation circuit includes a register for storing a chip enable signal and a second delay circuit connected to the output of said register, said read enable signal available at the output of said second delay circuit.
11. The logic circuit of claim 6 additionally comprising a clock generation circuit, said clock generation circuit for producing a clock signal that is twice the frequency of an externally supplied clock signal.
12. The logic circuit of claim 6 wherein said predetermined period of time is in the range of 0.5 to 4 clock periods of the externally supplied clock signal.
13. In combination, an output stage of a memory circuit and a control logic circuit for controlling its read latency time, said combination comprising:
a sense amplifier;
an output register responsive to said sense amplifier;
an output buffer responsive to said output register;
a delay circuit for receiving a read enable signal and for producing a plurality of values of the read enable signal each delayed by a predetermined period of time; and
a circuit for selecting one of said plurality of values as a control input to said output register and to said output buffer in response to externally supplied control signals.
14. The combination of claim 13 additionally comprising a signal generation circuit for generating the read enable signal from other externally supplied control signals.
15. The combination of claim 14 additionally comprising a buffer enable register connected between said circuit and said output buffer.
16. The combination of claim 15 additionally comprising an every-edge register and a gate, said gate having inputs connected to said circuit and said every-edge register and on output connected to said output register.
17. The combination of claim 16 additionally comprising a clock circuit for producing a clock signal, said clock signal being input to said buffer enable register, said output register, and said every-edge register.
18. A memory circuit, comprising:
a memory array;
write control and addressing logic connected to said memory array;
sense amplifiers connected to said memory array;
output registers connected to said sense amplifiers; and
read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of said output registers.
19. The memory circuit of claim 18 wherein said read output control logic includes a delay circuit for producing a plurality of values of a read enable signal, each value delayed by a predetermined period of time, and a multiplexer for selecting one of said plurality of values in response to at least one control signal, said selected value being input to said output registers.
20. The memory circuit of claim 19 additionally comprising a plurality of output buffers and wherein said read output control logic includes a buffer enable register connected between said multiplexer and said plurality of output buffers.
21. The memory circuit of claim 20 wherein said read output control logic includes an every-edge register and a gate, said gate having inputs connected to said every-edge register and said multiplexer and an output connected to said output registers.
22. The memory circuit of claim 21 wherein said read output control logic includes a clock circuit for producing a clock signal, said clock signal being input to said buffer enable register, said output registers, and said every-edge register.
23. The memory circuit of claim 22 wherein said delay circuit includes a plurality of series connected flip-flops clocked by said clock signal.
24. A system, comprising:
a controlling device;
a memory array;
write control and addressing logic connected to said memory array;
sense amplifiers connected to said memory array;
output registers connected to said sense amplifiers for outputting said read information; and
read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of said output registers.
25. The system of claim 24 wherein said controlling device is a microprocessor.
26. The system of claim 24 wherein said controlling device is an application specific integrated circuit.
27. A method for controlling the read latency time of a memory circuit, comprising the steps of:
delaying a read enable signal to produce a plurality of values, each value representative of said read enable signal delayed by a predetermined period of time; and
selecting one of said plurality of values in response to at least one control signal, said selected value being used to enable a read operation.
28. The method of claim 27 wherein said step of selecting includes the step of controlling the condition of a plurality of logic gates with a plurality of control signals.