1. A hydroxylapatite material containing tricalcium phosphate, obtained by converting a hard algae tissue free of organic compounds in an alkaline aqueous phosphate solution with addition of Mg2+ ions at increased temperature, wherein the microporous structure of the hard algae tissue starting materials remains intact in the material, and the material has a tricalcium phosphate content of 50 to 90% by weight, wherein the reaction temperature is between 230 and 250\xb0 C.
2. The hydroxylapatite material containing tricalcium phosphate as set forth in claim 1, with a tricalcium phosphate content of 70 to 90% by weight.
3. The hydroxylapatite material containing tricalcium phosphate as set forth in claim 1, wherein said hard algae tissue is obtained from lime-encrusting sea algae.
4. The hydroxylapatite material as claimed in claim 1, comprising at least one active ingredient.
5. The hydroxylapatite material as claimed in claim 4, wherein at least one of the active ingredient(s) comprises either a growth promoting compound or a growth inhibiting compound.
6. The hydroxylapatite material as claimed in claim 4, wherein at least one of the active ingredient(s) comprises an antibiotic, a chemotherapeutic, a tumor inhibiting compound, or a bone morphogenic protein.
7. A process for producing a hydroxylapatite material containing tricalcium phosphate obtained by converting a hard algae tissue free of organic compounds in an alkaline aqueous phosphate solution with addition of Mg 2+ ions in the form of a water-soluble magnesium salt at increased temperature, wherein the microporous structure of the hard algae tissue starting materials remains intact in the processed material, and the material has a tricalcium phosphate content of 50 to 90% by weight, wherein the reaction temperature is between 230 and 250\xb0 C.
8. The process as claimed in claim 7, wherein the water-soluble magnesium salt is magnesium nitrate.
9. The process as claimed in claim 7, wherein said magnesium salt is added in such quantity that a content of 50 to 90% by weight tricalcium phosphate is obtained in the processed material.
10. The process as claimed in claim 9, wherein said magnesium salt is added in a quantity of 5.5 to 6.0% by weight.
11. The process as claimed in claim 7, wherein (NH4)2HPO4 is used as phosphate.
12. The process as claimed in claim 7, wherein said conversion is carried out at a pH value between 8 and 11.
13. The process as claimed in claim 12, wherein the pH value is adjusted with NH3.
14. A process for producing a hydroxylapatite material containing tricalcium phosphate obtained by converting a hard algae tissue free of organic compounds in an alkaline aqueous phosphate solution with addition of Mg2+ ions in the form of a water-soluble magnesium salt at increased temperature, wherein the microporous structure of the hard algae tissue starting materials remains intact in the processed material, and the material has a tricalcium phosphate content of 50 to 90% by weight, wherein the reaction temperature is varied between 200 and 240\xb0 C.
15. The process as claimed in claim 14, wherein the reaction temperature is maintained respectively in cycles of ca. 200\xb0 and ca. 240\xb0 C.
16. The process as claimed in claim 15, wherein said cycles are two hours for each said temperature.
17. The process as claimed in claim 14, wherein said conversion is carried out at increased pressure.
18. The process as claimed in claim 15, wherein said conversion takes place in an autoclave coated with polytetrafluorethylene.
19. The process as claimed in claim 18, wherein said autoclave is filled to a maximum two thirds of capacity.
20. A hydroxylapatite material containing tricalcium phosphate, obtained by converting a hard algae tissue free of organic compounds in an alkaline aqueous phosphate solution with addition of Mg2+ ions at increased temperature, wherein the microporous structure of the hard algae tissue starting materials remains intact in the material, and the material has a tricalcium phosphate content of 70 to 90% by weight, wherein the reaction temperature is varied in cycles between 200 and 240\xb0 C.
21. The hydroxylapatite material containing tricalcium phosphate as set forth in claim 20, wherein said hard algae tissue is obtained from lime-encrusting sea algae.
22. The hydroxylapatite material as claimed in claim 20, comprising at least one active ingredient.
23. The hydroxylapatite material as claimed in claim 22, wherein at least one of the active ingredient(s) comprises either a growth promoting compound or a growth inhibiting compound.
24. The hydroxylapatite material as claimed in claim 22, wherein at least one of the active ingredient(s) comprises an antibiotic, a chemotherapeutic, a tumor inhibiting compound, or a bone morphogenic protein.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A programming method for a nonvolatile memory including memory cells configured to store more than one data bit according to an erase state and a plurality of program states for write data provided to a page buffer circuit, the method comprising:
programming respective memory cells using data stored in corresponding first and second latches of the page buffer;
performing verification read operations for the memory cells using different verification voltages respectively corresponding to the program states, and collecting verification read results for the verification read operations; and
updating the first and second latches in response to the collected verification read results.
2. The method of claim 1, further comprising:
initializing third latches respectively corresponding to the memory cells and selectively inverting data stored in the third latches corresponding to program-inhibited memory cells before collecting the verification read results for the verification read operations.
3. The method of claim 2, wherein the collecting the verification read results for the verification read operations comprises:
updating the data stored in third latches corresponding to memory cells having a threshold voltage higher than a first verification voltage; and
initializing data stored in third latches corresponding to memory cells to be programmed not to a program state corresponding to the first verification voltage among the third latches updated.
4. The method of claim 3, wherein the collecting the verification read results for the verification read operations comprises:
updating data stored in third latches corresponding to memory cells having threshold voltages higher than a second verification voltage; and
initializing data stored in third latches corresponding to memory cells to be programmed not to a program state corresponding to the second verification voltage among the third latches updated.
5. The method of claim 4, wherein the second verification voltage is higher than the first verification voltage.
6. The method of claim 4, wherein the collecting the verification read results for the verification read operations further comprises:
updating data stored in third latches corresponding to memory cells having threshold voltages higher than a third verification voltage.
7. The method of claim 6, wherein the third verification voltage is higher than the second verification voltage.
8. The method of claim 2, wherein the verification read operations are performed using different verification voltages having respective voltage levels that increase,
during each verification read operation having an associated verification voltage, data stored in third latches connected to memory cells having threshold voltages higher than the associated verification voltage is updated when the stored data is equal to an initialization value, and data stored in third latches, among the third latches updated, connected to memory cells programmed not to a program state corresponding to the associated verification voltage is initialized to the initialization value.
9. The method of claim 2, wherein the updating of the first and second data latches comprises:
updating the first and second data latches connected to third latches each having a value different from an initialization value such that memory cells connected to the third latches each having the value different from the initialization value are program-inhibited.
10. The method of claim 9, wherein the programming of respective memory cells using data stored in corresponding first and second latches of the page buffer, the performing of the verification read operations for the memory cells using different verification voltages respectively corresponding to the program states, and the collecting of the verification read results for the verification read operations constitute a program loop,
the program loop is iteratively performed until programming of the memory cells is passed,
data stored in of the third latches are set based on data stored in the first and second data latches as updated per each iteratively performed program loop, and
a program operation for each successive one of the iteratively performed program loops is controlled by data set to the third latches during a previous one of the iteratively performed program loops.
11. The method of claim 2, wherein the programming of respective memory cells using data stored in corresponding first and second latches of the page buffer, the performing of the verification read operations for the memory cells using different verification voltages respectively corresponding to the program states, and the collecting of the verification read results for the verification read operations constitute a program loop,
the program loop is iteratively performed until programming of the memory cells is passed, and
a program operation performed during a second program loop following a first program loop among the iteratively performed program loops is controlled by data set in the third latches during the first program loop.
12. The method of claim 1, further comprising:
before the programming the respective memory cells using data stored in corresponding first and second latches of the page buffer, loading write data to be programmed to the memory cells in the first and second latches.
13. The method of claim 1, further comprising:
before the programming of the respective memory cells using data stored in corresponding first and second latches of the page buffer, setting data in third latches depending on the data stored at the first and second latches,
wherein the programming of the respective memory cells is performed based on the data set in the third latches.
14. The method of claim 1, wherein the programming of respective memory cells using data stored in corresponding first and second latches of the page buffer, the performing of the verification read operation for the memory cells using different verification voltages respectively corresponding to the program states, and the collecting of the verification read results for the verification read operations constitute a program loop,
the program loop is iteratively performed until programming of the memory cells is passed, and
the method further comprises:
after the programming of the respective memory cells using data stored in corresponding first and second latches of the page buffer during a current program loop and before collecting the verification read results for the verification read operations during the current program loop, determining whether the programming of the respective memory cells during the current program loop is passed or failed based on verification read results collected during a previous program loop.
15. A nonvolatile memory, comprising:
a memory cell array including memory cells respectively connected to a plurality of bit lines; and
page buffers arranged in a page buffer circuit and respectively connected to the plurality of bit lines, wherein each page buffer comprises:
a latch; and
a first data latch and a second data latch respectively connected to one of the bit lines,
wherein during a verification read operation, latches connected to the plurality of bit lines are configured to collect verification read results over a plurality of verification read operations using different verification voltages respectively corresponding to different program states and update first data latches and second data latches corresponding to the latches depending on the collected verification read results.
16. The nonvolatile memory of claim 15, wherein the different program states correspond to different threshold voltage distribution ranges that programmed memory cells have.
17. The nonvolatile memory of claim 15, wherein the memory cells are programmed according to values of the latches, and
wherein the verification read operation is performed after the memory cells are programmed.
18. The nonvolatile memory of claim 15, wherein the memory cell array includes a plurality of cell strings arranged on a substrate in rows and columns,
wherein each of the plurality of cell strings includes at least one ground selection transistor, a plurality of memory cell transistors, and at least one string selection transistor stacked on the substrate along a direction perpendicular to the substrate, and
wherein the memory cells correspond to memory cell transistors placed in one row at the same height from the substrate and corresponds to memory cell transistors in one row.
19. An operating method of a nonvolatile memory which includes a plurality of memory cells respectively connected to a plurality of bit lines, first data latches respectively connected to the plurality of bit lines, and second data latches respectively connected to the plurality of bit lines, comprising:
programming the plurality of memory cells depending on data stored at the first and second data latches;
performing a first verification read operation for the plurality of memory cells using a first verification voltage and storing a result of the first verification read operation at latches respectively corresponding to the plurality of bit lines;
performing a second verification read operation for the plurality of memory cells using a second verification voltage and storing a result of the second verification read operation at the latches; and
updating the first data latches and the second data latches depending on the results of the first and second verification read operations stored at the plurality of latches.
20. The operating method of claim 19, wherein the result of the second verification read operation is additionally stored at the plurality of latches in addition to the result of the first verification read operation.