What is claimed is:
1. A nonvolatile semiconductor memory device comprising a memory cell, the memory cell comprising:
a pair of a first impurity-doped region and a second impurity-doped region formed in a silicon substrate;
a first insulating layer formed in the silicon substrate in such a manner as to at least cover a gap between the pair of the first and the second impurity-doped region;
a first gate formed on the first insulating layer;
a second insulating layer formed to cover the first gate;
a second gate formed on the insulating layer; and
a third gate insulated from both of the first gate and the second gate with insulating layers;
wherein:
the first gate is formed into a floating gate;
the second gate is connected with a word line;
each of the impurity-doped regions paired is connected with a bit line or a source line, and
surfaces of the first gate, which intersect the silicon substrate, are covered by insulating layers in both of a word line direction and a bit line direction, one of the insulating layers covering the first gate being a gate insulating layer for the first gate.
2. A nonvolatile semiconductor memory device comprising a memory cell, the memory cell comprising:
a first conductivity type well in a silicon substrate;
a second conductivity type semiconductor region having at least a pair of a first semiconductor region and a second semiconductor region, the second conductivity type semiconductor region being formed in the first conductivity type well;
a first gate insulating layer formed in the silicon substrate in such a manner as to at least cover a gap between the pair of the first and the second semiconductor region;
a first gate formed on the first gate insulating layer;
a second insulating layer formed to cover the first gate;
a second gate formed on the second insulating layer;
a third gate formed alongside the first gate in the silicon substrate with being insulated from the first gate and the second gate with the third insulating layer and a multilayer of at least the second insulating layer and a fourth insulating layer; and
a fifth insulating layer formed between the first gate and another first gate in a direction intersecting a direction in which the first gate and the third gate are aligned:
wherein:
one of surfaces of the first gate, which contacts with the second gate with the second insulating layer being formed therebetween, has a dented shape as viewed in sections which are perpendicular to the silicon substrate, one of the sections being taken in a direction extending from the first gate to the third gate and the other section being taken in a direction extending from the first gate to the fifth insulating layer.
3. The nonvolatile semiconductor memory device according to claim 2, wherein the fourth insulating layer is formed from an insulating layer material which is different from that used for forming the fifth insulating layer.
4. The nonvolatile semiconductor memory device according to claim 3, wherein the fourth insulating layer is of a silicon nitride film and the fifth insulating layer is of a silicon oxide film.
5. The nonvolatile semiconductor memory device according to claim 3, wherein the fourth insulating layer is of a silicon oxide film and the fifth insulating layer is of a silicon nitride film.
6. The nonvolatile semiconductor memory device according to claim 2, wherein a height of the first gate is below at least one of those of the fourth insulating layer and the fifth insulating layer.
7. The nonvolatile semiconductor memory device according to claim 2, wherein a height of the second gate is greater than that of the fourth insulating layer and equal to that of the fifth insulating layer.
8. The nonvolatile semiconductor memory device according to claim 2, wherein the height of the second gate is greater than that of the fifth insulating layer and equal to that of the fourth insulating layer.
9. The nonvolatile semiconductor memory device according to items claim 2, wherein one of the first gate, the second gate, and the third gate serves as an erase gate.
10. A nonvolatile semiconductor memory device comprising a memory cell, the memory cell comprising:
a first conductivity type well formed in a silicon substrate;
a second conductivity type semiconductor region which is a pair of a first semiconductor region and a second semiconductor region, the second conductivity type semiconductor region being formed in the first conductivity type well;
a first gate insulating layer formed in the silicon substrate in such a manner as to at least cover a gap between the first and the second semiconductor region of the second conductivity type semiconductor region;
a first gate formed on the first gate insulating layer;
a second insulating layer formed to cover the first gate;
a second gate formed on the second insulating layer;
a third gate adjacent to the first gate; and
a fourth insulating layer adjacent to the first gate in a direction intersecting a direction in which the first gate is adjacent to the third insulating layer;
wherein:
one of surfaces of the first gate, which contacts with the second gate with the second insulating layer being formed therebetween, has a dented shape as viewed in sections which are perpendicular to the silicon substrate, one of the sections being taken in a direction extending from the first gate to the third insulating layer and the other section being taken in a direction extending from the first gate to the fourth insulating layer.
11. The nonvolatile semiconductor memory device according to claim 10, wherein the third insulating layer is formed from an insulating layer material which is different from that used for forming the fourth insulating layer.
12. The nonvolatile semiconductor memory device according to claim 10, wherein the third insulating layer is of a silicon nitride film and the fourth insulating layer is of a silicon oxide film.
13. The nonvolatile semiconductor memory device according to claim 10, wherein the third insulating layer is of a silicon oxide film and the fourth insulating layer is of a silicon nitride film.
14. The nonvolatile semiconductor memory device according to claim 10, wherein a height of the first gate is below at least one of those of the third insulating layer and the fourth insulating layer.
15. The nonvolatile semiconductor memory device according to claim 10, wherein a height of the second gate is greater than that of the third insulating layer and equal to that of the fourth insulating layer.
16. The nonvolatile semiconductor memory device according to claim 10, wherein the height of the second gate is greater than that of the fourth insulating layer and equal to that of the third insulating layer.
17. The nonvolatile semiconductor memory device according to claim 10, wherein the first gate is a floating gate and the second gate serves both as a control gate and an erase gate.
18. The nonvolatile semiconductor memory device according to claim 1, wherein an interpoly dielectric film formed between the first gate and the second gate is formed from a high-k material.
19. A fabrication process of a nonvolatile semiconductor memory device, comprising:
a step of forming a first conductivity type well in a silicon substrate;
a step of forming in the first conductivity type well a second conductivity type semiconductor region which will be formed into a sourcedrain;
a step of forming a first gate in the silicon substrate via a first gate oxide film;
a step of forming a second gate in such a manner as to insulate the second gate from the first gate with a second insulating layer which covers the first gate;
a step of forming a third gate in such a manner as to insulate the third gate from the first gate and the second gate with a third insulating layer and a fourth insulating layer; and
a step of forming a fifth insulating layer adjacent to the first gate, wherein
the first gate is formed in such a manner that one of surfaces of the first gate, which contacts with the second gate via the second insulating layer, has a dented shape as viewed in sections which are perpendicular to the silicon substrate, one of the sections being taken in a direction extending from the first gate to the third gate and the other section being taken in a direction extending from the first gate to the fifth insulating layer.
20. The fabrication process of a nonvolatile semiconductor memory device according to claim 19, comprising:
a step of covering the third gate and the fourth insulating layer with the fifth insulating layer which is formed from a material different from that used for forming the fourth insulating layer after forming the third gate and a multilayer of the fourth insulating layer;
a step of processing the fifth insulating layer to form a space for forming therein the first gate;
a step of forming the first gate oxide film;
a step of forming the third insulating layer;
a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly;
a step of filling with a resist material the space remaining after the deposition of the first gate material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate becomes greater than at least one of those of the fourth insulating layer and the fifth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate in such a manner that a portion of the second insulating layer covering a dented surface of the first gate is not exposed.
21. The fabrication process of a nonvolatile semiconductor memory device according to claim 20, comprising:
a step of exposing the fourth insulating layer in such a manner as to leave the fifth insulating layer, the step being performed immediately before processing the fifth insulating layer to form the space in which the first gate will be formed.
22. The fabrication process of a nonvolatile semiconductor memory device according to claim 19, comprising:
a step of depositing and processing the fifth insulating layer;
a step of depositing a third gate material in such a manner as to fill a space of the fifth insulating layer;
a step of forming the third gate by an etch back in such a manner that a height of the third insulating layer is below that of the fifth insulating layer;
a step of covering the third gate and the fifth insulating layer with the fourth insulating layer;
a step of exposing the fifth insulating layer in such a manner as to leave the fourth insulating layer;
a step of processing the fifth insulating layer to form a space in which the first insulating layer will be formed;
a step of forming a first gate oxide film;
a step of forming the third insulating layer;
a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly;
a step of filling a space remaining after the deposition of the first gate material with a resist material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate becomes greater than at least one of those of the fourth insulating layer and the fifth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate in such a manner that a portion of the second insulating layer covering a dented surface of the first gate is not exposed.
23. The fabrication process of a nonvolatile semiconductor memory device according to claim 19, comprising:
a step of processing the fifth insulating layer for forming a space in which the first gate will be formed in such a manner that a height of a portion of the fourth insulating layer covering the space is below that of the fifth insulating layer;
a step of forming the first gate oxide film;
a step of forming the third insulating layer;
a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly;
a step of filling with a resist material a space remaining after the deposition of the first gate material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate becomes greater than that of the fifth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate by an etch back or a chemical mechanical polishing technique in a self alignment manner by taking advantage of a height difference between the fourth insulating layer and the fifth insulating layer.
24. A fabrication process of a nonvolatile semiconductor memory device, comprising:
a step of forming a first conductivity type well in a silicon substrate;
a step of forming in the first conductivity type well a second conductivity type semiconductor region which will be formed into a sourcedrain;
a step of forming a first gate on the silicon substrate via a first gate oxide film;
a step of forming a second gate in such a manner that the second gate is insulated from the first gate with a second insulating layer which covers the first gate; and
a step of forming a third insulating layer and a fourth insulating layer which are adjacent to the first gate;
wherein:
the first gate is formed in such a manner that one of surfaces of the first gate, which contacts with the second gate via the second insulating layer, has a dented shape as viewed in sections which are perpendicular to the silicon substrate, one of the sections being taken in a direction extending from the first gate to the third insulating layer and the other section being taken in a direction extending from the first gate to the fourth insulating layer.
25. The fabrication process of a nonvolatile semiconductor memory device according to claim 24, comprising:
a step of depositing the third insulating layer;
a step of processing the third insulating layer;
a step of forming a sourcedrain diffusion layer by using the processed third insulating layer as a mask;
a step of covering the third insulating layer with the fourth insulating layer;
a step of exposing the third insulating layer in such a manner as to leave the fourth insulating layer;
a step of further processing the third insulating layer to form a space in which the first gate will be formed;
a step of forming a first gate oxide film;
a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly;
a step of filling with a resist material a space remaining after the deposition of the first gate material;
a step of forming the first gate by an etch back in an self alignment manner so that a height of the first gate is below at least one of the third insulating layer and the fourth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate in such a manner as to avoid exposing a portion of the second insulating layer covering a dented surface of the first gate.
26. The fabrication process of a nonvolatile semiconductor memory device according to claim 24, comprising:
a step of processing the third insulating layer for forming a space in which the first gate will be formed in such a manner that a height of a portion of the fourth insulating layer covering the space is below that of the third insulating layer;
a step of forming the first gate oxide film;
a step of depositing a first gate material in such a manner as to avoid filling up the space perfectly;
a step of filling with a resist material a space remaining after the deposition of the first gate material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate becomes greater than that of the third insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate by an etch back or a chemical mechanical polishing technique in a self alignment manner taking advantage of a height difference between the third insulating layer and the fourth insulating layer.
27. The fabrication process of a nonvolatile semiconductor memory device according to claim 24, comprising:
a step of depositing the third insulating layer;
a step of processing the third insulating layer;
a step of covering the third insulating layer with a dummy gate material;
a step of forming a dummy gate;
a step of forming a sourcedrain diffusion layer by using the dummy gate and the third insulating layer as a mask;
a step of covering the dummy gate and the third insulating layer with the fourth insulating layer;
a step of exposing the dummy gate in such a manner that the third insulating layer and the fourth insulating layer are remained;
a step of removing the dummy gate;
a step of forming a first gate oxide film;
a step of depositing a first gate material in such a manner as to avoid filling up a space formed by the removal of the dummy gate;
a step of filling with a resist material a space remaining after the deposition of the first gate material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate is below at least one of the third insulating layer and the fourth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate in such a manner that a portion of the second insulating layer covering a dented surface of the first gate is not exposed.
28. The fabrication process of a nonvolatile semiconductor memory device according to claim 27, comprising:
a step of removing the dummy gate in such a manner that a height of the third insulating layer is below that of the fourth insulating layer;
a step of forming the first gate oxide film;
a step of depositing the first gate material in such a manner as to avoid filling up a space formed by the removal of the dummy gate perfectly;
a step of filling with a resist material a space remaining after the deposition of the first gate material;
a step of forming the first gate in a self alignment manner by an etch back so that a height of the first gate is below that of the fourth insulating layer;
a step of depositing the second insulating layer;
a step of depositing a second gate material; and
a step of processing the second gate by an etch back or a chemical mechanical polishing technique in a self alignment manner taking advantage of a height difference between the third insulating layer and the fourth insulating layer.
29. The fabrication process of a nonvolatile semiconductor memory device according to claim 19, comprising a step of forming an interpoly dielectric film formed between the first gate and the second gate from a high-k material such as tantalum pentoxide.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A housing closing cover comprising:
a carrier element having a generally planar bottom surface to be positioned in direct abutment against a mating component and having an opening in said carrier element;
a fluid seal mounted in said opening of said carrier element, said seal having a static annular axial sealing lip facing in the axial direction of said opening adjacent an edge of said opening, said axial sealing lip extending axially outwardly from said planar bottom surface of said carrier element to provide a static face seal between said housing and the mating component, and including an annular radial sealing lip attached to said axial sealing lip and extending in a radial direction from said axial sealing lip for sealing a member projecting through said opening, and wherein said radial sealing lip extends axially inwardly in relation to said planar bottom surface and is supported for angular and radial movement relative to said carrier element without significantly impairing the sealing established by said radial sealing lip about the member projecting through the opening.
2. The housing cover of claim 1, wherein said fluid seal includes a fusion zone connecting said radial sealing lip to said axial sealing lip and enabling said angular and radial movement of said radial sealing lip through flexing of said fusion zone.
3. The housing cover of claim 2 wherein said fusion zone is tapered having a wave form.
4. The housing cover of claim 1 including a rigid ring mounted on said sealing lip opposite and annularly about said sealing lip.
5. The housing cover of claim 4 wherein said rigid ring is molded in place in said fluid seal.
6. The housing cover of claim 1 wherein a portion of said radial sealing lip is radially aligned with said planar bottom surface of said carrier element.
7. The housing cover of claim 6 wherein a wave shaped fusion zone extends coplanar with said planar bottom surface of said carrier element to connect said static face seal to said axial sealing lip.
8. The housing cover of claim 1 wherein said carrier element includes an axially angled region adjacent said opening.
9. The housing cover of claim 1 including a flexible retainer spring mounted on said fluid seal opposite and annularly about said radial sealing lip.