1. An improved hand mixer comprising:
at least one cap and a container;
said container further comprising an enlarged upper portion and a smaller central portion,
said enlarged portion further comprising an opening through which substances to be mixed can be placed into said container,
said at least one cap further comprising
an inner surface adapted to fit over said opening of said container to form a seal, said cap characterized by one or more protrusions extending from said interior surface of said cap into said container,
a barrier extending from said interior surface of said cap around said protrusions and downwardly into said lower portion of said container, said barrier having an outer surface engaging at least a portion of the inner surface of said lower portion of said container such that said barrier inhibits substances to be mixed from migrating into said upper portion of said container outside said barrier during operation of said improved hand mixer.
2. The improved hand mixer according to claim 1 further comprising said protrusions extending from said interior surface of said cap are integrally formed with said cap.
3. The improved hand mixer according to claim 1, at least one of said protrusions comprising a helical ridge.
4. The improved hand mixer according to claim 3, said helical ridge extending along the entire length of said at least one protrusion.
5. The improved hand mixer according to claim 1 in which said one or more protrusions comprises a plurality of protrusions.
6. The hand mixer according to claim 5 said protrusions further comprise one or more disks spaced longitudinally along said protrusions.
7. The hand mixer according to claim 5 comprising said protrusions being arranged in a grid pattern.
8. The hand mixer according to claim 5 comprising protrusions being arranged in staggered-row pattern.
9. The hand mixer according to claim 1 wherein at least one of said one or more protrusions is cylindrical in shape.
10. The hand mixer according to claim 1 wherein at least one of said one or more protrusions is fluted in shape.
11. The hand mixer according to claim 1 wherein at least one of said one or more protrusions is cross-shaped.
12. The hand mixer according to claim 1 wherein said container further comprises at least two openings.
13. The hand mixer according to claim 1 wherein at least one of said one or more protrusions can be attached and detached from said inner surface of said cap.
14. The hand mixer according to claim 5 wherein said plurality of protrusions can be attached and detached from said inner surface of said cap.
15. The hand mixer according to claim 1 wherein the outer surface of said barrier fits tightly against at least a part of the inner surface of said container.
16. The hand mixer according to claim 1 wherein said container has a lower portion comprising a base, said base having an outer diameter larger than the outer diameter of said central portion.
17. The hand mixer according to claim 1 wherein the inner diameter of said opening is larger than the outer diameter of said barrier.
18. The hand mixer 1 according to claim 17 wherein the lowest extremity of said barrier contacts and fits snugly within said inner surface of said container, and the inner diameter of said container increases from the point of contact with said lowest extremity of said barrier upwardly to a maximum diameter at said opening.
19. A hand mixer comprising a container and two caps, said container being generally cylindrical and comprising two openings at opposing ends of said container, the diameter of said container being greater at said openings and decreasing at a central portion;
each said cap being configured to securely seal opening during operation, each said cap further comprising a plurality of pointed protrusions situated on an inner surface of said cap and extending into said container when said cap is covering said opening,
each said cap further comprising a barrier forming a complete loop around said plurality of pointed protrusions and extending into said container, the lower portion of said barrier being in contact with the inner surface of said central portion of said container to form a seal around the inner surface of said central portion of said container when each respective said cap is securely attached to an opening of said container.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A microprocessor, comprising:
an execution unit configured to operate on instructions and data;
a cache memory subsystem coupled to said execution unit;
wherein said cache memory subsystem includes:
a plurality of storage blocks, each configured to store a plurality of data units, wherein each of said plurality of storage blocks is configured to be accessed asynchronously, such that each of said plurality of storage blocks is configured to be accessed without respect to a clock signal;
a plurality of tag units coupled to said plurality of storage blocks, wherein each of said plurality of tag units is configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within a corresponding one of said plurality of storage blocks, wherein each of said plurality of tag units is configured to be accessed synchronously.
2. The microprocessor as recited in claim 1 further comprising a cache control coupled to provide a plurality of cache access requests to said plurality of tag units.
3. The microprocessor as recited in claim 1, wherein said plurality of tag units are accessible synchronously in response to a clock signal.
4. The microprocessor as recited in claim 1, wherein each of said plurality of storage blocks includes a plurality of storage sub-blocks each independently accessible.
5. The microprocessor as recited in claim 4, wherein said plurality of storage sub-blocks are accessible asynchronously in response to a read signal and a write signal.
6. The microprocessor as recited in claim 5, wherein said cache control further comprising a pulse generator coupled to said plurality of storage sub-blocks and configured to generate said read signal and said write signal.
7. The microprocessor as recited in claim 6, wherein said pulse generator is further configured to generate said read signal in response to receiving a read request having an address which matches one of said address tag values stored within a given one of said plurality of tag units.
8. The microprocessor as recited in claim 6, wherein said pulse generator is further configured to generate said write signal in response to receiving a write request having an address which matches one of said address tag values stored within a given one of said plurality of tag units.
9. The microprocessor as recited in claim 6, wherein said pulse generator is programmable, wherein a delay between two successive read signals and two successive write signals to a same storage sub-block is adjustable.
10. A cache memory subsystem, comprising:
a plurality of storage blocks, each configured to store a plurality of data units, wherein each of said plurality of storage blocks is configured to be accessed asynchronously, such that each of said plurality of storage blocks is configured to be accessed without respect to a clock signal;
a plurality of tag units coupled to said plurality of storage blocks, wherein each of said plurality of tag units is configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within a corresponding one of said plurality of storage blocks, wherein each of said plurality of tag units is configured to be accessed synchronously.
11. The cache subsystem as recited in claim 10 further comprising a cache control coupled to provide a plurality of cache access requests to said plurality of tag units.
12. The cache subsystem as recited in claim 10, wherein said plurality of tag units are accessible synchronously in response to a clock signal.
13. The cache subsystem as recited in claim 10, wherein each of said plurality of storage blocks includes a plurality of storage sub-blocks each independently accessible.
14. The cache subsystem as recited in claim 13, wherein said plurality of storage sub-blocks are accessible asynchronously in response to a read signal and a write signal.
15. The cache subsystem as recited in claim 14, wherein said cache control further comprising a pulse generator coupled to said plurality of storage sub-blocks and configured to generate said read signal and said write signal.
16. The cache subsystem as recited in claim 14, wherein said pulse generator is further configured to generate said read signal in response to receiving a read request having an address which matches one of said address tag values stored within a given one of said plurality of tag units.
17. The cache subsystem as recited in claim 14, wherein said pulse generator is further configured to generate said write signal in response to receiving a write request having an address which matches one of said address tag values stored within a given one of said plurality of tag units.
18. The cache subsystem as recited in claim 14, wherein said pulse generator is programmable, wherein a delay between two successive read signals and two successive write signals to a same storage sub-block is adjustable.
19. A method of accessing a cache memory subsystem, said method comprising:
accessing, asynchronously with respect to any clock signal, a plurality of storage blocks, each configured to store a plurality of data units;
storing a plurality of tags each including an address tag value which corresponds to a given unit of data stored within said plurality of storage blocks; and
synchronously accessing a plurality of tag units.
20. The method as recited in claim 19 further comprising generating a read signal and a write signal for asynchronously accessing said plurality of storage blocks.
21. The method as recited in claim 19 further comprising generating said read signal and said write signal with a programmable delay between successive read signals and successive write signals to a same storage sub-block of a given one of said plurality of storage blocks.
22. A microprocessor, comprising:
an execution unit configured to operate on instructions and data;
a cache memory subsystem coupled to said execution unit;
wherein said cache memory subsystem includes:
means for synchronously receiving a read request matching an address tag value within a tag unit;
means for generating a read access signal corresponding to said read request;
means for providing said read signal and accessing, asynchronously with respect to any clock signal, a storage sub-block corresponding to said address tag value.
23. A computer system, comprising:
a system memory configured to store instructions and data;
a microprocessor coupled to said system memory and configured to execute said instructions and to operate on said data;
wherein said microprocessor includes a cache memory subsystem including:
a plurality of storage blocks, each configured to store a plurality of data units, wherein each of said plurality of storage blocks is configured to be accessed asynchronously, such that each of said plurality of storage blocks is configured to be accessed without respect to a clock signal;
a plurality of tag units coupled to said plurality of storage blocks, wherein each of said plurality of tag units is configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within a corresponding one of said plurality of storage blocks, wherein each of said plurality of tag units is configured to be accessed synchronously.