1. An information processing device which transmits and receives information to and from other devices via a network, comprising:
(a) a memory storing a plurality of objects as nodes of a hierarchical tree structure, wherein:
(i) each object is denoted as a particular sub-tree of the hierarchical tree structure, each object comprising one or more application nodes, one or more data nodes, and zero or more objects as sub-nodes,
(ii) each sub-tree is given a unique label that represents corresponding nodes of the hierarchical tree structure, the unique label including (A) name information showing node names from a highest order node of the hierarchical tree structure to a highest order node of the sub-tree, the name information being continuous and (B) a storing position indicating a location of the sub-tree on the network;
(iii) each application node including application logic for calling-up, writing, deleting, or partially changing one or more data nodes of the respective application node’s object;
(b) a transmitting and receiving section transmitting and receiving information expressed in an external language to and from other devices via the network, the transmitting and receiving section receiving an HTTP request comprising: a particular label expressing a designated sub-tree, and an identification of an application node of the designated sub-tree; and
(c) an engine section which functions as a universal interface and includes:
a first translating section including a deserializing section which via the network acquires the designated sub-tree and the identified application node of the designated sub-tree from the HTTP request and translates the designated sub-tree into information expressed in an internal language while preserving a tree structure of the designated sub-tree,
a control section executing the application logic of the identified application node of the designated sub-tree, and
a second translating section including a serializing section translating a sub-tree stored in the memory into the external language while preserving a tree structure of the stored sub-tree;
wherein the information processing device enables a user to change contents of the one or more data nodes during the execution of a program of the information processing device that accesses the plurality of objects.
2. The information processing device of claim 1, wherein the unique label is expressed by a URI.
3. The information processing device of claim 1, wherein the engine section includes a determining section which determines whether the designated sub-tree is stored internally or externally of the information processing device; and upon determining the designated sub-tree is stored in external storage, translating the request into the external language at the second translating section; and upon determining the designated sub-tree is stored in internal storage of the information processing device, outputting the request to the transmitting and receiving section.
4. The information processing device of claim 1, wherein the control section’s execution of the application logic comprises adding a data node to the object at the designated sub-tree.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A tristate buffer circuit operable to be switched into a high impedance state in response to a first configuration signal (CSI) comprising:
a tristate buffer (TBUF) having an input, an output and a tristate control input, said tristate buffer (TBUF) outputting a signal (BUF OUT) corresponding to said signal on said input in a normal mode and outputting a high impedance signal in a high impedance mode as controlled by said tristate control input;
a delay stage (DEL) having a input receiving an input signal (BUF IN) and an output connected to said input of said tristate buffer (TBUF) for delaying said input signal (BUF IN);
a gating stage (GS) having inputs receiving said input signal (BUF IN), a delayed signal (BUF IN DEL, BUF OUT) by said delay stage (DEL) and an asynchronous tristate signal (3ST) indicating that the buffer (TBUF) is to be switched into the high impedance state, and an output connected to said tristate control input of said tristate buffer (TBUF) providing a configuration signal (CSI), said gating stage (GS) operable to set said configuration signal (CSI) to select said high impedance mode only when said tristate signal (3ST) is set and said input signal (BUF IN) and said delayed signal (BUF IN DEL, BUF OUT) have the same logic levels indicating that no signal transition of said input signal (BUF IN) propagates within said delay stage (DEL);
wherein said gating stage (GS) includes a latch, which is only set if said tristate signal (3ST) is set and said input signal (BUF IN) and said output signal (BUF OUT) have the same logic levels.
2. The tristate buffer circuit according to claim 1, wherein:
said input signal (BUF IN) is a clock signal; and
said delay stage (DEL) has a delay less than half a clock period of said clock signal.
3. The tristate buffer circuit according to claim 1, wherein:
said input signal (BUF IN) is a clock signal having a period T; and
said delay stage (DEL) has a delay longer than (2nT)2 and shorter than (2n+1)T2, where n is an integer with n\u22670.
4. The tristate buffer circuit according to claim 1, further comprising:
a regenerative loop (RL) coupled to said output of said tristate buffer (TBUF) maintaining said output signal (BUF OUT) when said tristate buffer (TBUF) is switched into said high impedance mode.
5. The tristate buffer circuit according to claim 1, wherein:
said delayed input signal consists of an output (BUF IN DEL) of said delay stage (DEL).
6. The tristate buffer circuit according to claim 1, wherein:
said delayed input signal consists of said output (BUF OUT) of said tristate buffer (TBUF).