1. A memory device for use with an external circuit, the memory device comprising:
at least one first integrated circuit die including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core and configuring a data rate for transferring data between the memory cells and the first interface circuit; and
at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit.
2. The memory device as set forth in claim 1, further comprising:
a plurality of the first integrated circuit dies.
3. The memory device as set forth in claim 1, further comprising:
a plurality of the second integrated circuit dies.
4. A memory device for use with an external circuit. the memory device comprising:
at least one first integrated circuit die including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core;
at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit;
a first package housing the at least one first integrated circuit die; and
a second package housing the at least one second integrated circuit die.
5. The memory device as set forth in claim 1, further comprising:
a single package housing the first and second integrated circuit dies.
6. A memory device for use with an external circuit, the memory device comprising:
at least one first integrated circuit die including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core;
a plurality of second integrated circuit dies, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; and
a single package housing the at least one first integrated circuit die and housing the plurality of second integrated circuit dies.
7. A memory device for use with an external circuit, the memory device comprising:
a plurality of first integrated circuit dies including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core;
at least one second integrated circuit die, electrically coupled to the plurality of first integrated circuit dies, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit; and
a single package housing the plurality of the first integrated circuit dies and housing the at least one second integrated circuit die.
8. A memory device for use with an external circuit, the memory device comprising:
a plurality of first integrated circuit dies including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core;
at least one second integrated circuit die. electrically coupled to the plurality of first integrated circuit dies, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit;
a first package for housing the plurality of the first integrated circuit dies; and
a second package for housing the at least one second integrated circuit die.
9. A memory device for use with an external circuit, the memory device comprising:
at least one first integrated circuit die including,
a memory core comprising a plurality of memory cells, and
a first interface circuit including a first interface for accessing the memory cells of the memory core;
at least one second integrated circuit die, electrically coupled to the first integrated circuit die, comprising a second interface for accessing the memory core via the first interface circuit and for interfacing the memory core to the external circuit;
wherein the second interface of the at least one second integrated circuit die is further for converting protocols between the external circuit and the first interface of the first integrated circuit die.
10. The memory device as set forth in claim 9, wherein:
the protocols comprise,
a first protocol, and
a second protocol which is different from the first protocol.
11. The memory device as set forth in claim 10, wherein:
the first protocol comprises a synchronous protocol; and
the second protocol comprises an asynchronous protocol.
12. The memory device as set forth in claim 10, wherein:
the first protocol comprises a custom protocol; and
the second protocol comprises an industry standard protocol.
13. The memory device as set forth in claim 1, wherein:
the first interface circuit is further for providing a read operation to the memory cells.
14. The memory device as set forth in claim 1, wherein:
the first interface circuit is further for providing a write operation to the memory cells.
15. The memory device as set forth in claim 1, wherein:
the first interface circuit is further for providing activating, pre-charging and refreshing operations to the memory cells.
16. The memory device as set forth in claim 1, wherein the first integrated circuit die comprises:
a plurality of memory banks for partitioning the memory cells.
17. The memory device as set forth in claim 16, wherein the memory banks comprise:
a plurality of sub-arrays arranged in a distributed bank architecture across a plurality of physical sections such that a physical section of the memory cells comprises a plurality of sub-arrays associated with different ones of the memory banks.
18. The memory device as set forth in claim 1, wherein the memory cells comprise:
at least one non-volatile memory cell.
19. The memory device as set forth in claim 1, wherein the memory cells comprise:
at least one volatile memory cell.
20. A memory device for use with an external circuit, the memory device comprising:
a first integrated circuit die including,
a memory core including a plurality of memory cells, and
a first interface circuit having a first interface and coupled to the memory cells, for dynamically configuring an internal data rate for transferring data between the memory cells and the first interface circuit; and
a second integrated circuit die, electrically coupled to the first integrated circuit die, including a second interface for accessing data from the memory core via the first interface circuit and for interfacing said memory core to the external circuit.
21. The memory device as set forth in claim 20, wherein:
the memory device further comprises an internal data bus for coupling data between the first integrated circuit die and the second integrated circuit die; and
the internal data bus has a configurable data width.
22. The memory device as set forth in claim 20, wherein the internal data rate comprises:
a configurable amount of data for pre-fetching.
23. The memory device as set forth in claim 20, wherein the first integrated circuit die further comprises:
at least one input for programming said data width for said internal data bus.
24. The memory device as set forth in claim 20, further comprising:
an external data bus, having an external data rate, for accessing data external to the memory device, wherein the internal data rate can be dynamically selected so as to be compatible with the external data rate.
25. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between a DDR2 SDRAM protocol and a DDR3 SDRAM protocol.
26. The memory device as set forth in claim 9, wherein said second interface of said second integrated circuit die for converting between a first timing specification of a DDR2 SDRAM protocol and a second timing specification of a DDR2 SDRAM protocol.
27. The memory device as set forth in claim 1, wherein the data rate is an internal data rate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for producing an over-running decoupler that is configured to transmit rotary power between a rotary member and a hub, the over-running decoupler comprising a one-way clutch having a clutch spring, a carrier that is coupled to the clutch spring and at least one spring that resiliently couples the carrier to the hub, the method comprising:
establishing a desired fatigue life of the at least one spring;
establishing a design deflection of the at least one spring during resonance, wherein deflection of the at least one spring at the design deflection during resonance does not reduce a fatigue life of the at least one spring below the desired fatigue life; and
preventing resonance in the over-running decoupler by controlling a maximum deflection of the at least one spring such that the maximum deflection is less than or equal to the design deflection.
2. The method of claim 1, wherein the design deflection is a maximum deflection of the at least one spring during resonance that does not reduce the fatigue life of the at least one spring below the desired fatigue life.
3. The method of claim 1, wherein the design deflection is established at least partly based on a rotational inertia of at least one device that is driven through the over-running decoupler.
4. The method of claim 1, wherein the design deflection is established at least partly based on a peak torque of one or more devices driven through the over-running decoupler.
5. The method of claim 1, further comprising establishing a peak drive torque of a device that is to receive rotary power from the over-running decoupler and wherein the maximum deflection of the at least one spring is greater than a deflection of the at least one spring when a torque having a magnitude that is equal to the peak drive torque is transmitted through the over-running decoupler.
6. The method of claim 1, wherein the clutch spring comprises a helical torsion spring having coils that are disposed concentrically about a rotational axis of the over-running decoupler.
7. A method for operating a drive system having an endless power transmitting element and an over-running decoupler, the over-running decoupler comprising a hub, a rotary member and a one-way clutch between the hub and the rotary member, the one-way clutch comprising a carrier, a clutch spring and one or more springs disposed between the carrier and the hub, the clutch spring having a first end, which is engaged to the carrier, the clutch spring being configured to be drivingly coupled to the rotary member, the method comprising:
operating the drive system under a first set of operating conditions to cause coupling of the clutch spring to the rotary member to facilitate transmission of torque through the over-running decoupler; and
decoupling the over-running decoupler in response to deflection of the at least one spring by an amount that is greater than or equal to a predetermined spring deflection;
wherein the predetermined spring deflection is selected to inhibit onset of a resonant condition in the at least one spring.
8. The method of claim 7, wherein the at least one spring comprises a helical coil spring that is disposed concentrically about a rotational axis of the over-running decoupler.
9. The method of claim 7, wherein the clutch spring has a second end on a side that is opposite the first end, the second end being contacted by the hub to coil at least a portion of the clutch spring in a direction away from the rotary member to thereby initiate the decoupling of the over-running decoupler when the amount by which the at least one spring has deflected is greater than or equal to the predetermined spring deflection.
10. The method of claim 7, wherein the rotary member comprises a pulley, a roller or a sprocket.
11. The method of claim 7, wherein the predetermined spring deflection is selected to provide the at least one spring with a predetermined fatigue life.
12. A method for producing an over-running decoupler that is configured to transmit rotary power between a rotary member and a hub, the over-running decoupler comprising a clutch having a clutch spring, a carrier that is coupled to the clutch spring and at least one spring that resiliently couples the carrier to the hub, the method comprising:
establishing a desired fatigue life of the at least one spring;
establishing a design torque that may be transmitted through the at least one spring during resonance, wherein transmission of the design torque through the at least one spring during resonance does not reduce a fatigue life of the at least one spring below the desired fatigue life; and
preventing resonance in the over-running decoupler by controlling a maximum torque transmitted through the decoupler such that the maximum torque is less than or equal to the design torque.
13. The method of claim 12, wherein the design torque is a maximum torque that may be transmitted through the at least one spring during resonance without reducing the fatigue life of the at least one spring below the desired fatigue life.
14. The method of claim 12, further comprising establishing a peak drive torque of a device that is to receive rotary power from the over-running decoupler and wherein the maximum torque that is transmitted through the over-running decoupler is greater than the peak drive torque.
15. The method of claim 12, wherein the design torque is established at least partly based on a rotational inertia of at least one device that is driven through the over-running decoupler.
16. The method of claim 12, wherein the design torque is established at least partly based on a peak torque of one or more devices driven through the over-running decoupler.
17. The method of claim 12, wherein the clutch spring comprises a helical torsion spring having coils that are disposed concentrically about a rotational axis of the over-running decoupler.